Hi,
I have a question about AM1808 USB.
We are using USB as peripheral and have a question about Bulk In Transaction.
In AM1808 TRM(spruh82a) page.1588 "34.2.7.1.2.1.2 Operation", it said as follow:
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When data is to be transferred over a Bulk IN pipe, a data packet needs to be loaded into the FIFO and
the PERI_TXCSR register written to set the TXPKTRDY bit (bit 0). When the packet has been sent, the
TXPKTRDY bit will be cleared by the USB controller and an interrupt generated so that the next packet
can be loaded into the FIFO.
If double packet buffering is enabled, then after the first packet has been
loaded and the TXPKTRDY bit set, the TXPKTRDY bit will immediately be cleared by the USB controller
and an interrupt generated so that a second packet can be loaded into the FIFO.
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If double packet buffer is disabled,
I guess we can know when the packet transimittion are completed by the interrupt.
But if double packet buffer is enabled, how to know the first packet transmission are completed?
In above description of double buffering, it seem that interrupt will be generated when first packet has been loaded(not transfer completion).
In the case which the single buffer is enough for packet transfer but double packet buffer is enabled,
the interrupt will be generated for second packet(but in this case there are no second packet)
before the previous packet transmission complete. Is there any method to know the first packet transfer completion?
best regards,
g.f.