I am reposting this into the community. I already posted this as a response to my previous post but not sure whether I'll get the attention as the previous post is marked as "Answered"
Here is the original post:
https://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/493574/1786813#1786813
I followed the example code provided by Sivaraj and moved it my project. There are some differences in clock dividers and clock direction but I exactly followed the steps of the example. I tried avoiding the example function calls as that needs to bring in a large number of header files that conflict with the set of header files already exist in the project. Here is the extract of the code that enables EDMA channel 3, FIFO and McASP1 for TX using serializer 1. We need to send bit and HF clocks out as opposed the example. I configured the FS and Clock CTL registers appropriately.
I still do not see the output on the data pins as well as the Data bus register corresponding to McASP1 (0x1d06000) does not get modified by DMA writes. However I do not see any buffer under run in McASP (bit 0 and bit 6 of XSTAT are cleared). FS and CLK signals are coming out from the DMA pins though there is no data output.
I set the link address in the param set to be 0xffff (only one param set is used and testing only for a single transfer for simplicity) and once the transfer is initialized the A CNT, B CNT ... are changed to 0. Also I see event 3 in ER is set as well. If I understand correctly DMA transfer has completed (as Param set is loaded with 0 after the transfer). What I can't understand is the reason for not see date in the Data bus port (0x1D06000) which actually updates its content with data in the given example example.
I believe I captured all the major configuration steps in the following code. Any help on this is highly appreciated.
/* Function corresponding to EDMA3Init*
* ------------------------------------------
* ------------------------------------------
* ------------------------------------------
* /
/* clear the Event missed register*/
edma3ccRegs->EMCR = 0xFFFFFFFF;
edma3ccRegs->EMCRH = 0xFFFFFFFF;
edma3ccRegs->QEMCR = 0xFFFFFFFF;
edma3ccRegs->ECR = 0xFFFFFFFF;
edma3ccRegs->EECR = 0xFFFFFFFF;
/*Clear CCERR register */
edma3ccRegs->CCERRCLR = 0xFFFFFFFF;
/* For EDMA enable DMA 0-64 channels in the DARE regions
*
*/
edma3ccRegs->CCERRCLR = 0xFFFFFFFF;
/*Enable DMA shadow regions
*
* */
edma3ccRegs->DRA[1].DRAE = 0xFFFFFFFF;
edma3ccRegs->DRA[1].DRAEH = 0xFFFFFFFF;
/* Initilize DMA queue number registers
*
* */
int queue_num = 0;
int i;
for (i = 0; i< 32; i++)
{
edma3ccRegs->DMAQNUM[i>>3] &= ~(0x7 << ( (i % 8u)*4u ));
edma3ccRegs->DMAQNUM[i>>3] |= (0x7 & queue_num) << ( (i % 8u)*4u );
}
/* Initilize QDAM queue number registers
*
* */
edma3ccRegs->QRAE[1] = 0xFFFFFFFF;
for (i = 0; i< 8; i++)
{
edma3ccRegs->QDMAQNUM &= ~(0x7 << ( i*4u ));
edma3ccRegs->QDMAQNUM |= (0x7 & queue_num) << ( i*4u );
}
/* Enable DMA channel 3 for McASP1 TX
* ----------------------------------------------
* ---------------------------------------------
* */
int qnum = 0;
edma3ccRegs->DRA[1].DRAE |= 0x01u << 3 ; /* For channel 3 */
edma3ccRegs->DMAQNUM[0] &= ~(0x7 << ( (3u % 8u) * 4u )); ; /* For channel 3 */
edma3ccRegs->DMAQNUM[0] |= (0x7 & qnum << ( (3u % 8u) * 4u )); /* For channel 3 */
/* Enable shadow region for channel 3 interrupts
*
*/
edma3ccRegs->DRA[1].DRAE |= 0x01u << 3 ; /* For channel 3 */
/* Enable channel interrupts
*
*/
//edma3ccRegs->IESR |= 0x01u << 3; /* For channel 3 */
/*Enable Event interrupts
*
*/
edma3ccRegs->SHADOW[1].IESR |= 0x01u << 3 ; /* For channel 3 */
/* Set Channel 1 Param Set
*
*
*/
edma3ccRegs->PARAMSET[3].OPT = 0;
edma3ccRegs->PARAMSET[3].OPT &= ~(0x0003F000u);
//edma3ccRegs->PARAMSET[1].OPT |= ((((0x0003F000u) >> (0x0000000Cu)) & (1)) << (0x0000000Cu));
edma3ccRegs->PARAMSET[3].OPT |= 0x2 << 8 | 0x2; /* 32 bit words No chaning is done. Interrupts are disabled,
A sync transfer, FWID = 16bits */
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[3].SRC = (Uint32)&Audio;
edma3ccRegs->PARAMSET[3].DST = (Uint32)0x01D06000;
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[3].A_B_CNT = 0x00400004;
edma3ccRegs->PARAMSET[3].CCNT = 0x00000001; /* i*/
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[3].SRC_DST_BIDX = 0x0000004; /* no jumps in the address updates */
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[3].SRC_DST_CIDX = 0x00000000;
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[3].LINK_BCNTRLD = 0x0000ffff; // This the last transfer. No linking is done.
/* Now configure the McASP
* -----------------------------------------------------------
* -----------------------------------------------------------
*/
/* Reset McASP1
*
*/
mcasp->regs->XGBLCTL = 0x00;
int num_ser =1;
int words_per_ser = 1;
/* FIFO Enable */
WFIFOCTL_MCASP1 = ( num_ser | (( num_ser * words_per_ser) <<(8u)) );
WFIFOCTL_MCASP1 |= 0x00010000u; /* enable FIFO */
/* Configure MCASP 1
*
*/
mcasp->regs->XMASK = 0xffffffff; // No padding used
mcasp->regs->XFMT = 0x00008070; // MSB 16bit, 0-delay, no pad, CFGBus
mcasp->regs->AFSXCTL = 0x00000112; // 2TDM, 1bit Rising edge INTERNAL FS, word
mcasp->regs->ACLKXCTL = 0x000000AF; // ASYNC, Rising INTERNAL CLK, div-by-16
mcasp->regs->XCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
mcasp->regs->XTDM = 0x00000003; // Slots 0,1
mcasp->regs->SRCTL1 = 0x000D; // MCASP1.AXR1[1] Transmits to --> peripheral
mcasp->regs->PFUNC = 0; // Pins are all MCASP, none are GPIO
mcasp->regs->PDIR = 0xfe00ffff; // All data pins, AXR1[0-15] are outputs, as are ACLKX1 and AFSX1.
mcasp->regs->XINTCTL = 0x0F; // Not used
/* Follow the exact procedure to enabel DMA for TX
*
*
*/
/*McASP tx enable
*
*/
mcasp->regs->XGBLCTL |= 0x800u; /* release state machine */
while (mcasp->regs->XGBLCTL & 0x800u != 0x800u);
mcasp->regs->XGBLCTL |= 0x1000u; /* release Frame Sync Generator */
while (mcasp->regs->XGBLCTL & 0x1000u != 0x1000u);
/* reset High frequency clock */
mcasp->regs->XGBLCTL |= 0x200u; /* release state machine */
while (mcasp->regs->XGBLCTL & 0x200u != 0x200u);
/* enabel bit clock */
mcasp->regs->XGBLCTL |= 0x100u; /* release state machine */
while (mcasp->regs->XGBLCTL & 0x100u != 0x100u);
/* Enable DMA event */
edma3ccRegs->SHADOW[1].SECR = 0x01u << 3 ; /* For channel 1 */
edma3ccRegs->EMCR |= 0x01u << 3 ; /* For channel 1 */
edma3ccRegs->SHADOW[1].EESR |= 0x01u << 3 ; /* For channel 1 */
/* Enable Serializers */
mcasp->regs->XSTAT = 0xFFFF;
mcasp->regs->XGBLCTL |= 0x400u; /* release serializers */
while (mcasp->regs->XGBLCTL & 0x400u != 0x400u);
/* wait while XDATA is cleared */
while (mcasp->regs->XSTAT & 0x20u );
/* Enable McASP */
mcasp->regs->XGBLCTL |= 0x800u; /* release state machine */
while (mcasp->regs->XGBLCTL & 0x800u != 0x800u);
mcasp->regs->XGBLCTL |= 0x1000u; /* release Frame Sync Generator */
while (mcasp->regs->XGBLCTL & 0x1000u != 0x1000u);