I’m having trouble with the starterware and I’m looking for some help. I am trying to add some functionality to the McASP example project, but before I do that, I need to get the existing project to support stereo mic input and stereo line output. As best I can tell, the current example does not do so.
The problem I see is that the buffers that are brought in from the AIC via the McASP / DMA are mono. The 16-bit data in the buffers has non-zero samples in the even words and zero samples in the odd words. A similar thing seems to be going on at the output. The McASP demo blindly copies the received samples from the DMA receive buffer to the DMA transmit buffer to do an input to output loopback. And even though every other sample is zero, the audio goes to both speakers. And, it doesn’t matter whether I connect a microphone only to the left mic input or to the right mic input, the audio is output to both speakers. It is as if the two mic inputs are combined into a single PCM channel, and the “even” samples are fed to both audio outputs whereas the “odd” samples are discarded.
I want to take you through my line of thinking because that might trigger some thoughts of your own about where I have gone wrong in my thinking.
The LCDK mic input is connected to the AIC’s MI3L/LINE3L and MIC$/LINE3R inputs. I’ll refer to them as MIC3L and MIC3R from here forward for simplicity.
From the AIC block diagram (in the data sheet), I see that MIC3L feeds both the left and right A/D. Same goes for MIC3R. So if the user wishes to operate in stereo mode, he/she must program the AIC to do so. The registers to program are.
Page 0 / Register 17: MIC3L/R to Left ADC Control Register and
Page 0 / Register 18: MIC3L/R to Right ADC Control Register
As best I can tell, register 17 should be 0x0f and register 18 should be 0xf0. The example code sets both to zero, which would send MIC3L+MICR to both the left and right ADCs. But regardless of whether I leave the settings alone or I change them to 0x0f and 0xf0, the data in the rxOut buffer(s) is the same in that even 16-bit samples are non-zero and odd 16-bit samples are zero.
At the analog output side of the AIC, there is a similar architecture in that the left and right channels can be summed and the resulting mono signal can be sent to both the left and right outputs.
The setting of Page 0 / Register 41: DAC Output Switching Control Register places the left and right DAC outputs on the DAC_L1 and DAC_L2 paths respectively. These paths can be summed into both left and right outputs.
The registers that control this are:
Page 0 / Register 82: DAC_L1 to LEFT_LOP/M Volume Control Register
Page 0 / Register 85: DAC_R1 to LEFT_LOP/M Volume Control Register
Page 0 / Register 89: DAC_L1 to RIGHT_LOP/M Volume Control Register
Page 0 / Register 92: DAC_R1 to RIGHT_LOP/M Volume Control Register
I don’t see any issues in the sample code’s programming of these registers.
It has been suggested that the problem could lie in the EDMA3 setup. I didn’t see any problems there. I also looked at the McASP setup and didn’t see any problems there either. But I am not an expert in using any of these peripherals so please don’t assume that just because I didn’t see a problem that one does not exist.