Hi,
Please help to see if information from IC's designer can be obtained for this question.
We used assembly routine to test core execution speed, and although the cpu runs at 300mhz, for each us’s 300 cycles we could only access ARM local RAM for 6 times, with both I/D cache enabled and unaltered from default state.
As in ARM’s 926EJ-S (ARM DDI 0198E) there is TCM used as a fast memory interface. Information related to TCM is not seen in L138 documents, except that in TRM’S interconnect diagram we see ARM RAM is connected to cache and cpu via SCR2.
1. Please provide more information on how TI implements TCM. What is the cycle delay for accessing 8K RAM, and shared 128K RAM and DDR2, respectively?
2. Please also test with the attached assembly, which we place in 8K RAM, with stack allocated at 128K shared RAM. We verified at clocking module multiplier/dividers and the clock for CPU is indeed 300mhz. Is the speed of execution (6 RAM assesses per us) normal? And how could it be so slow even with cache enabled?
Lencho
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