OMAPL138 McBSP CLKGDV setting

Hi,

In the following document:

"www.ti.com/.../omap-l138.pdf"

In section 6.16 it states:

'If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.'

What is the consequence if a value of zero is used? I've tried it set to zero and it appears to work.

Not being able to set it to zero does limit the max speed that can be used especially when running at 1.0V (PLL_SYSCLK2 max is 75MHz, if CLKGDV has to be 1 or more this means max McBSP rate is 37.5MHz).

Thanks

Nigel