Hello
I came from here:
Now my customer is trying to understand the mDDR Usage Note descriptions in errata.
I understood the workaround for this issue, but my customer is saying if they could have more detailed information about this issue.
Considering the above Mulul's answer, if SRR command is *optional* on mDDR, it would be possible for mDDR to mis-understand incoming MSR command as SRR command at the first auto initialization sequence. If this condition is met, the memory controller on OMAP-L138 does not generate READ command at the next expected timing and finally mDDR could get stuck in SRR state. This is overall understanding on this issue. Correct, right ? Please let me confirm my understanding is correct or not.
If the above understanding is correct, we have some further questions :
1. The above *optional* is confusing. Can we understand this problem can happen on some mDDR parts *strictly* supporting JEDEC-compliant SRR feature including its command sequence and timing? Or, Does it mean some mDDR parts (I'm not sure such mDDR parts are existing in the market) which is roughly following JEDEC spec about SRR command might go into the problem ?
2. Why does the second MRS command (stated as a workaround) surely make mDDR exiting from SRR state ? Is this defined in JEDEC spec ? I know TI recommends to ask memory vendors when applying this workaround. So I think TI is expecting this scenario, but is not sure about this. This is possible work around -- Correct ?
Best Regards,
Naoki Kawada