Hi,
I have been working for a bit on getting a simple example up and running with the goal of sharing some space in the shared memory between the ARM and DSP. I base my example from the integration example of the rCSL, which I'm trying to port to SYS/BIOS for both arm and dsp. I can succesfully fire the interrupts from both sides.
The arm configures 2 ISR tied to:
CSL_FINST(sysRegs->CHIPSIG, SYSCFG_CHIPSIG_CHIPSIG0, ASSERT);
CSL_FINST(sysRegs->CHIPSIG, SYSCFG_CHIPSIG_CHIPSIG1, ASSERT);
and the dsp configures 2 isrs tied to
CSL_FINST(sysRegs->CHIPSIG, SYSCFG_CHIPSIG_CHIPSIG2, ASSERT);
CSL_FINST(sysRegs->CHIPSIG, SYSCFG_CHIPSIG_CHIPSIG3, ASSERT);
I have a custom plataform in which neither the arm or the dsp maps the SDRM.
Sometime when I run, actually quire often, I get the following exception from the DSP
Instruction fetch exception
{module#20}: line 256: error {id:0xb0000, args:[0x0, 0x1180dfb0]}
xdc.runtime.Error.raise: terminating execution
This is preceded by the following (not sure if it helps)
A0=0x0 A1=0x11803200
A2=0x0 A3=0x1180d94c
A4=0x0 A5=0x1180d91c
A6=0x0 A7=0x1180c064
A8=0x1180e158 A9=0x1180dbb4
A10=0x118087b4 A11=0x2
A12=0x0 A13=0x1180dfb0
A14=0x0 A15=0x0
A16=0x2 A17=0x0
A18=0x118087b4 A19=0x7f0000
A20=0x0 A21=0x10
A22=0x118058f0 A23=0x49011040
A24=0x2 A25=0x110000
A26=0x2 A27=0x110000
A28=0x0 A29=0x1180d2a7
A30=0x1 A31=0x11800b80
B0=0x0 B1=0x118098b4
B2=0x2 B3=0x1180e4f0
B4=0x0 B5=0x0
B6=0x0 B7=0x1180dfb0
B8=0x1180d313 B9=0x1180e430
B10=0x1180911c B11=0x10
B12=0x0 B13=0x10
B14=0x11800000 B15=0x1180e480
B16=0x0 B17=0x1180e480
B18=0xffffffff B19=0xffffffff
B20=0xfffffff7 B21=0x0
B22=0x66666666 B23=0x30666666
B24=0x50d0f7f7 B25=0x8880248d
B26=0xffffffe1 B27=0x1180d3cd
B28=0x2 B29=0x0
B30=0xf B31=0x1180083c
NTSR=0x1000f
ITSR=0x11808670
IRP=0x11807e54
SSR=0x0
AMR=0x11809eb6
RILC=0x0
ILC=0x0
Exception at 0xfffffffc
EFR=0x2 NRP=0xfffffffc
Internal exception: IERR=0x1
My shared memory is created like this:
#define SHARED_MEM_ADDRESS 0x80018000
#define SHARED_ARRAY_SIZE 8
typedef struct{
volatile int ARRAY_1[SHARED_ARRAY_SIZE];
volatile int ARRAY_2[SHARED_ARRAY_SIZE];
volatile int ARRAY_3[SHARED_ARRAY_SIZE];
volatile int ARRAY_4[SHARED_ARRAY_SIZE];
} sharedCpuVars;
typedef volatile sharedCpuVars *sharedCpuVarsPtr;
// Pointer to Shared (DSP/ARM) Variables
sharedCpuVarsPtr sharedVars = (sharedCpuVarsPtr)(SHARED_MEM_ADDRESS);