Hello,
We have a very tightly integrated embedded system using the OMAP L138 (2 OMAP L138's actually). The system uses DMA transfers for SPI, UART comms, and McBSP (for inter-core messaging), as well as memory-to-memory transfers.
Is there any GPIO pin (or if must a register), that can provide information on the idle/busy time of the transfer controllers (TC0 and 1 for CC0) and TC0 for CC1?
Currently we can only see that we are not seeing missed events, but we have no idea about the margins we have. It would allow for us to have confidence that the EDMA engine is not close to being overloaded, especially for the SPI peripheral transfers were there is no FIFO and the turnaround time for each SPI transfer is 744ns. We have our time critical transfers on queue 0 of CC0 and the others on queue 1 of CC0. Memory-to-memory transfers are handled by CC1.
Thanks