Hi All !
I have a parallel 12-bit ADC interfaced to my OMAP-L137 via GPIO pins. This ADC is clocked to sample at 5 MHz. In other words, every 0.2 usec, my data are ready and available in the GPIO registers. Once ready, I need to transfer one array of 4 bytes from the GPIO registers (data and control signals values) to a destination buffer in memory (I already validated the feasibility to make a DMA transfer from the GPIO registers).
I configured my EDMA paramSet with an A-synchonization (ACNT=4, BCNT=1024, CCNT=1), supposing I transfer each element of 4 bytes (each triggered by a periodic event) in a buffer of 1024 * 4 bytes.
Thus, I need to trigger a DMA transfer (of 4 bytes) at the frequency of 5 MHz, i.e each 0.2usec.
My question is thus, is there any minimum time required between to successive DMA transfers, triggered by 2 successive events? Will I be able to make the DMA transfer of 4 bytes within real 0.2usec, knowing that after 204.8 usec (1024 * 0.2 usec), I must have 1024 * 4 bytes successfully copied in memory?
I could not find the information in the EDMA3 datasheet... Does anymore could help me to clarify this feasibility?
Thanks in advance for your support,
Mai.