We are using a OMAPL138 with Linux on the ARM side and BIOS 5.41.10.36 on the DSP side. We have a FPGA connected via the EMIFA bus. We are counting on the EMIFA_CLK to run the internal logic on the FPGA. The reads and writes to registers in the FPGA are asynchronous.
The problem is that the EMIFA_CLK output is not toggling. It just goes high and stays there. Looking at the PINMUX registers with the debugger on the DSP side, shows PINMUX6 = 0x00110001. The least significant 4 bits correspond to the EMIFA_CLK pin, and a value of 1 enables the EMIFA_CLK function (according the PinMux Utility). The OMAPL138 TRM implies that this pin is driven by the PLL once the device is released from reset. Why aren't we seeing any output?
From the OMAPL138 Technical Reference Manual: