I am trying to put a custom DA830 board into a low power mode. When low power is required, a standby micro asserts RESET to the DA830. The reset is a so-called "power-on reset" because TRST is pulled low through 4.7K.
My problem is that the board seems to go into two different low power states with a 90 mW difference between them (as measured at the board's +5V input). Whether the board powers down to X mW or X + 90 is apparently random. The variation in power is on the +3.3V supply, not the +1.3V supply. Without an easy way to measure current drawn by the SDRAMs, I can only guess that the difference is in the SDRAM state when the DA830 is reset.
I have attempted to do the following to put the board into low power mode, but have not gotten rid of the randomness:
1) The ARM, which is running Linux, resets other devices on the board, then sends a command to the DSP to request power down.
2) The DSP, running code from L3RAM, clears the ARM's LRST bit in psc0->MDCTL[LPSC_ARM] to reset the ARM (to keep it from accessing the SDRAMs)
3) (Additionally, I have tried adding lpscDisable to disable the ARM's power domain)
4) The DSP disables hardware interrupts, the idea being that an SDRAM access might reawaken the RAMs.
5) The DSP sets the SR_PD bit in the SDRAM Refresh Control Register to select power-down as opposed to self-refresh.
6) The DSP sets the LP_MODE bit in the SDRAM Refresh Control Register to power down the RAMs.
7) The DSP drives a GPIO to request a reset from the micro.
8) The micro asserts reset to the DA830
Do you see anything wrong with my understanding? Is there anything else I need to do to make sure the SDRAMs are in a low power state when the DA830 is held in reset? Or is the 90 mW variation (measured at +5VIN) unlikely to be due to the SDRAMs?