I am using an OMAP-L138 evaluation board for developing a C6746 application. The ARM processor is not involved...it sits in a loop monitoring the serial port.
I have set up the uPP for the simplest possible use as a receive only on a single channel with a slow clock. From the uPP status registers, it seems to do everything I wanted it to do...I set it up with a line of 8192 bytes, 2 pages, and a line offset of 8192.
I clock it and watch the status registers for the byte count and line count incrementing each 64 bytes, and the current address as well, exactly where it appears in the map file. The EOLI and EOWI bits appear as they ought at the right times when I reach the 1st line and 2nd line.
Only problem is that nothing gets written to memory, except in one. If I use shared RAM at 0x8000 0000, it writes the data OK (except for some reason not the 1st 256 bytes??). If I split L1D to 16K of cache and 16K of data, it does not work If I use L2 RAM, it does not work. Are there some special tricks that need to be taken to allow the DMA of the uPP to write data? Or some limitations that I have not found? (I tried doing a cache invalidate when using L2RAM, and viewing L2RAM directly with the debugger, and no data enters it...I fill the whole buffer with a pattern 0xDEAD so that it will be clear if it is written).
No interrupts are enabled. I see in the UPISR register a value of 0x20 ( reserved bit set). When the end of line occurs, it changes to 0x34...that is, end of line, but also, the internal bus error condition. I could not find any documentation on what causes the latter.
Any help would be much appreciated. I have a feeling that I am missing some small point.
Thanks