Hello,
I have got a problem when I implement a FIR with coefficients greater than 25.
It's OK for a FIR with 24 coefficients but when I put 25 coefficients or more, the filter doesn't work.
I join configuration file and c code of the filter.
I have got a Spectrum Digital Omap-L137 EVM board and I use CCS 6.
thank you for your help.
best regards
/*------------------------------------------------------------------------ *
* \file evmomapl137_aic3106_init.c *
* \brief implementation of a aic3106 driver for the OMAP-L137 EVM *
* ----------------------------------------------------------------------- */
// ======== Includes =======================================================
#include "evmomapl137_aic3106.h"
#include "evmomapl137_i2c.h"
// ======== Definitions ====================================================
#define AIC3106_I2C_ADDR 0x18 // I2C address
// ======== EVMOMAPL137_AIC3106_rset =======================================
// write a register on the AIC3106
void EVMOMAPL137_AIC3106_rset( Uint16 regnum, Uint16 regval )
{
Uint8 cmd[2];
cmd[0] = regnum & 0x007F; // 7-bit Device Address
cmd[1] = regval; // 8-bit Register Data
EVMOMAPL137_I2C_write( AIC3106_I2C_ADDR, cmd, 2 );
return;
}
/* ------------------------------------------------------------------------ *
* Initialize AIC3106 codec by writing to its control registers *
* *
* AIC3106.MCLK = PLL1705.SCK02 *
* FS = ( AIC3106.MCLK * K ) / ( 2048 * P ) *
* *
* or a FS=[48 kHz] & MCLK=[22.5792 MHz] *
* : 48kHz = ( 22.5792 MHz * K ) / ( 2048 * P ) *
* : P = 2, K[J.D] = 8.7075 *
* ------------------------------------------------------------------------ */
// ======== EVMOMAPL137_AIC3106_init =======================================
// configuration codec registers. Please see AIC3106 documentation for explanation (TLV320AIC3106)
void EVMOMAPL137_AIC3106_init( Uint16 adc_gain, Uint16 dac_atten, Uint16 fsAIC3106 )
{
/* configure AIC3106 */
EVMOMAPL137_AIC3106_rset( AIC3106_PAGESELECT, 0 ); // select page 0
EVMOMAPL137_AIC3106_rset( AIC3106_RESET, 0x80 ); // reset AIC31
/* configure AIC3106 register 2 and 7 for setup sampling rate */
switch( fsAIC3106 ) // default 8kHz
{
case FS_8000_HZ:
EVMOMAPL137_AIC3106_rset( 2, 0xAA ); // ADC/DAC sample rate = f(s)/6 = MCLK/(128*Q)/6
EVMOMAPL137_AIC3106_rset( 7, 0x0A ); // codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_12000_HZ:
EVMOMAPL137_AIC3106_rset( 2, 0x66 ); // ADC/DAC sample rate = f(s)/4 = MCLK/(128*Q)/4
EVMOMAPL137_AIC3106_rset( 7, 0x0A ); // codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_16000_HZ:
EVMOMAPL137_AIC3106_rset( 2, 0x44 ); // ADC/DAC sample rate = f(s)/3 = MCLK/(128*Q)/3
EVMOMAPL137_AIC3106_rset( 7, 0x0A ); // codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_24000_HZ:
EVMOMAPL137_AIC3106_rset( 2, 0x22 ); // ADC/DAC sample rate = f(s)/2 = MCLK/(128*Q)/2
EVMOMAPL137_AIC3106_rset( 7, 0x0A ); // codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
case FS_48000_HZ:
EVMOMAPL137_AIC3106_rset( 2, 0x00 ); // ADC/DAC sample rate = f(s)/1 = MCLK/(128*Q)/1
EVMOMAPL137_AIC3106_rset( 7, 0x0A ); // codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
default:
EVMOMAPL137_AIC3106_rset( 2, 0xAA ); // ADC/DAC sample rate = f(s)/6 = MCLK/(128*Q)/6
EVMOMAPL137_AIC3106_rset( 7, 0x0A ); // codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
break;
}
/* configure AIC3106 registers */
EVMOMAPL137_AIC3106_rset( 3, 0x22 ); // 3 PLL A <- [PLL=OFF][Q=4][P=2]
EVMOMAPL137_AIC3106_rset( 4, 0x20 ); // 4 PLL B <- [J=8]
EVMOMAPL137_AIC3106_rset( 5, 0x6E ); // 5 PLL C <- [D=7075]
EVMOMAPL137_AIC3106_rset( 6, 0x23 ); // 6 PLL D <- [D=7075]
EVMOMAPL137_AIC3106_rset( 8, 0x00 ); // 8 Audio InterFace Control A <- [BCLK=Slave][MCLK=Slave]
EVMOMAPL137_AIC3106_rset( 9, 0x00 ); // 9 Audio InterFace Control B <- [I2S mode][16 bit]
EVMOMAPL137_AIC3106_rset( 10, 0x00 ); // 10 Audio InterFace Control C <- [Data oFFset=0]
EVMOMAPL137_AIC3106_rset( 12, 0x00 ); // 12 Audio InterFace Control C <- [Data oFFset=0]
EVMOMAPL137_AIC3106_rset( 15, adc_gain); // 15 left ADC PGA Gain <- [Mute=OFF][Gain=0dB]
EVMOMAPL137_AIC3106_rset( 16, adc_gain); // 16 Right ADC PGA Gain <- [Mute=OFF][Gain=0dB]
EVMOMAPL137_AIC3106_rset( 17, 0x0F); // 17 MIC3L/R to left ADC <- [MIC3L=0dBGain][MIC3R=NotConnect]
EVMOMAPL137_AIC3106_rset( 18, 0xF0 ); // 18 MIC3L/R to Right ADC <- [MIC3L=NotConnect][MIC3R=0dBGain]
EVMOMAPL137_AIC3106_rset( 19 ,0x04 ); // 19 LINE1L to left ADC <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
EVMOMAPL137_AIC3106_rset( 22, 0x04 ); // 22 LINE1R to Right ADC <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
EVMOMAPL137_AIC3106_rset( 25, 0x40 ); // 25 MICBIAS <- [MICBIAS=2.0V]
EVMOMAPL137_AIC3106_rset( 27,0 ); // 27 left AGC B <- [OFF]
EVMOMAPL137_AIC3106_rset( 30, 0 ); // 30 Right AGC B <- [OFF]
EVMOMAPL137_AIC3106_rset( 37, 0xE0 ); // 37 DAC Power & Output Dvr <- [leftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd]
EVMOMAPL137_AIC3106_rset( 38, 0x10 ); // 38 High Power Output Dvr <- [HPRCOM=SingleEnd][ShortCircuit=OFF]
EVMOMAPL137_AIC3106_rset( 43, dac_atten ); // 43 left DAC Digital Volume <- [Mute=OFF][Gain=0dB]
EVMOMAPL137_AIC3106_rset( 44, dac_atten ); // 44 Right DAC Digital Volume <- [Mute=OFF][Gain=0dB]
EVMOMAPL137_AIC3106_rset( 47, 0x80 ); // 47 DAC_L1 to HPLOUT Volume <- [Routed]
EVMOMAPL137_AIC3106_rset( 51, 0x09 ); // 51 HPLOUT Output <- [Mute=OFF][Power=ON]
EVMOMAPL137_AIC3106_rset( 58, 0 ); // 58 HPLCOM Output <- []
EVMOMAPL137_AIC3106_rset( 64, 0x80 ); // 64 DAC_R1 to HPROUT Volume <- [Routed]
EVMOMAPL137_AIC3106_rset( 65, 0x09 ); // 65 HPROUT Output <- [Mute=OFF][Power=ON]
EVMOMAPL137_AIC3106_rset( 72, 0 ); // 72 HPRCOM Output <- []
EVMOMAPL137_AIC3106_rset( 82, 0x80 ); // 82 DAC_L1 to left_LOP/M Volume <- [Routed]
EVMOMAPL137_AIC3106_rset( 86 ,0x09 ); // 83 LINE2R to left_LOP/M Volume <- []
EVMOMAPL137_AIC3106_rset( 92, 0x80 ); // 92 DAC_R1 to RIGHT_LOP/M Volume <- [Routed]
EVMOMAPL137_AIC3106_rset( 93, 0x09 ); // 93 RIGHT_LOP/M Output <- [Mute=OFF][Power=ON]
EVMOMAPL137_AIC3106_rset( 101, 0x01 ); // 101 GPIO Control Register B <- [CODEC_CLKIN = CLKDIV_OUT]
EVMOMAPL137_AIC3106_rset( 102, 0 ); // 102 Clock Generation Control <- [PLLCLK_IN and CLKDIV_IN use MCLK]
return;
}
/*------------------------------------------------------------------------ *
* \file evmomapl137_mcasp.c *
* \brief configure and initialize McASP1 for interrupt-based i/o *
* ----------------------------------------------------------------------- */
// ======== Includes =======================================================
#include "evmomapl137_mcasp.h"
// ======== Private Defines and Macros ====================================
extern void intcVectorTable( void );
extern cregister volatile unsigned int CSR; // control status register
extern cregister volatile unsigned int ICR; // interrupt clear register
extern cregister volatile unsigned int IER; // interrupt enable register
extern cregister volatile unsigned int ISTP; // interrupt
#define INTC_INTMUX1 *(unsigned int*)(0x01800104)
static MCASP_Handle mcasp;
/* ------------------------------------------------------------------------ *
* *
* McASP1 is in MASTER mode. *
* BCLK & WCLK come from McASP1 *
* DIN is used by write16/write32 *
* DOUT is usec by read16/read32 *
* *
* ------------------------------------------------------------------------ */
// ======== EVMOMAPL137_PCASP_init =========================================
// setup McASP registers for Interrupt mode and I2S mode
void EVMOMAPL137_MCASP_init( Int32 fsMcASP )
{
/* enable write access to PINMUX and CFG registers in KICK0R and KICK1R */
KICK0R = 0x83E70B13; // Kick0 register and data (unlock)
KICK1R = 0x95A4F1E0; // Kick1 register and data (unlock)
/* write to the PINMUX registers to enable the McASP1 and I2C0 */
PINMUX8 = 0x01122000u; // McASP1 and I2C0
PINMUX11 = 0x11100000u; // McASP1
PINMUX12 = 0x11111111u; // McASP1
PINMUX13 = 0x00111111u; // McASP1
KICK0R = 0;
KICK1R = 1;
/* reset MCASP1 */
mcasp = &MCASP_MODULE_1;
mcasp->regs->GBLCTL = 0; // reset
mcasp->regs->RGBLCTL = 0; // reset RX
mcasp->regs->XGBLCTL = 0; // reset TX
mcasp->regs->PWRDEMU = 1; // free-running
/* ------------------------------------------------------------------------------------ *
* NOTE: ROR 16-bits enabled for both XMT/RCV. SLOT SIZE = 16 bits, 1-bit delay for Rx *
* clock and frame sync generated by extern oscillator of 24576 KHz *
* Tx and Rx synchronized *
* ------------------------------------------------------------------------------------ */
/* conFiguration RX mode I2S */
mcasp->regs->RMASK = 0xFFFFFFFF; // no padding used
mcasp->regs->RFMT = 0x0001807C; // MSB First, align left, slot=16bits, 1-bit delay, ROR 16-bits
mcasp->regs->AFSRCTL = 0x00000112; // frame sync generated externally, FS/word, 2 SLOT TDM = I2S
mcasp->regs->RTDM = 0x00000003; // slots 0,1
mcasp->regs->RINTCTL = 0x00000000; // not used
mcasp->regs->RCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
/* configuration TX mode I2S */
mcasp->regs->XMASK = 0xFFFFFFFF; // no padding used
mcasp->regs->XFMT = 0x0001807C; // MSB First, align left, slot=16bits, 1-bit delay, ROR 16-bits
mcasp->regs->AFSXCTL = 0x00000112; // frame sync generated externally, FS/word, 2 SLOT TDM = I2S
mcasp->regs->XTDM = 0x00000003; // slots 0,1
mcasp->regs->XINTCTL = 0x00000020; // enable interrupt on transmit
mcasp->regs->XCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
/* configuration clock operation */
switch( fsMcASP ) // set up sampling rate - default 8kHz
{
case FS_8000_HZ:
mcasp->regs->ACLKRCTL = 0x000000A7; // rising INTERNAL CLK,(From tx side)
mcasp->regs->ACLKXCTL = 0x000000A7; // ASYNC, Rising INTERNAL CLK, div-by-96
break;
case FS_12000_HZ:
mcasp->regs->ACLKRCTL = 0x000000A9; // rising INTERNAL CLK,(From tx side)
mcasp->regs->ACLKXCTL = 0x000000A9; // ASYNC, Rising INTERNAL CLK, div-by-64
break;
case FS_16000_HZ:
mcasp->regs->ACLKRCTL = 0x000000AF; // rising INTERNAL CLK,(From tx side)
mcasp->regs->ACLKXCTL = 0x000000AF; // ASYNC, Rising INTERNAL CLK, div-by-48
break;
case FS_24000_HZ:
mcasp->regs->ACLKRCTL = 0x000000AD; // rising INTERNAL CLK,(From tx side)
mcasp->regs->ACLKXCTL = 0x000000AD; // ASYNC, Rising INTERNAL CLK, div-by-32
break;
case FS_48000_HZ:
mcasp->regs->ACLKRCTL = 0x000000AF; // rising INTERNAL CLK,(From tx side)
mcasp->regs->ACLKXCTL = 0x000000AF; // ASYNC, Rising INTERNAL CLK, div-by-16
break;
default:
mcasp->regs->ACLKRCTL = 0x000000A7; // rising INTERNAL CLK,(From tx side)
mcasp->regs->ACLKXCTL = 0x000000A7; // ASYNC, Rising INTERNAL CLK, div-by-8
break;
}
mcasp->regs->AHCLKRCTL = 0x00000000; // INT CLK (From tx side)
mcasp->regs->AHCLKXCTL = 0x00000000; // INT CLK, div-by-4
/* conFiguration serializers (5 = xmit , 0 = rcv) */
mcasp->regs->SRCTL5 = 0x000D; // MCASP1.AXR1[5] --> DIN
mcasp->regs->SRCTL0 = 0x000E; // MCASP1.AXR1[0] <-- DOUT
/* conFiguration pin Function and direction */
mcasp->regs->PFUNC = 0; // All MCASPs
mcasp->regs->PDIR = 0x14000020; // ACLK and AFSX out_datas pins
mcasp->regs->DITCTL = 0x00000000; // not used
mcasp->regs->DLBCTL = 0x00000000; // not used
mcasp->regs->AMUTE = 0x00000000; // not used
return;
}
// ======== EVMOMAPL137_MCASP_start ==========================================
// enable the audio clocks and verification that each bit is properly set
void EVMOMAPL137_MCASP_start( void )
{
/* starting sections oF the McASP */
mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON; // HS Clk
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON; // HS Clk
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );
mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON; // Clk
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON; // Clk
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );
mcasp->regs->XSTAT = 0x0000FFFF; // clear all
mcasp->regs->RSTAT = 0x0000FFFF; // clear all
mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON; // serialize
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON; // serialize
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );
/* write a 0, so that no underrun occurs aFter releasing the state machine */
mcasp->regs->XBUF5 = 0;
mcasp->regs->RBUF0 = 0;
mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON; // state Machine
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON; // state Machine
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );
mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON; // frame Sync
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON; // frame Sync
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );
/* start by sending a dummy write */
while( ! ( mcasp->regs->SRCTL5 & 0x10 ) ); // check For Tx ready
mcasp->regs->XBUF5 = 0;
return;
}
// ======== EVOMAPL137_intr_init ===========================================
// enable the interrupt mode and configuration PINMUX for McASP1
void EVMOMAPL137_MCASP_isr( void )
{
/* configuration interrupt register of McASP */
CSR = 0x0000; // disable interrupts globally while initializing
INTC_INTMUX1 = 0x3D; // associate event 61 (McASP event) with interrupt 4 by writing 61 into LSBs of INTMUX1
ISTP = (unsigned int)intcVectorTable;
ICR = 0xFFF0; // clear bits in interrupt flag register IFR
IER |= 0x0012; // enable RTDX interrupts NMI (bit 1) and INT4 (bit 4)
CSR |= 0x0001; // enable interrupts globally
return;
}
/*------------------------------------------------------------------------ *
* \file evmomapl137_line.c *
* \brief Read sample from AIC3106 and write sample to AIC3106 *
* ----------------------------------------------------------------------- */
// ======== Includes =======================================================
#include "evmomapl137.h"
#include "evmomapl137_aic3106.h"
#include "evmomapl137_mcasp.h"
// ======== WriteDataToLineout ============================================
// wait for receive ready and copy the sample to the output register
void WriteDataToLineout( Int16 dataIn )
{
while (!( MCASP1_SRCTL5 & 0x10 ));
MCASP1_XBUF5_32BIT = dataIn | 0x00000000; // out the sample to line out and headphone channel left
while (!( MCASP1_SRCTL5 & 0x10 ));
MCASP1_XBUF5_32BIT = dataIn | 0x00000000; // out the sample to line out and headphone channel right
return;
}
// ======== WriteDataToLineoutStereo ======================================
// wait for receive ready and copy the sample to channels using slot 0,1
void WriteDataToLineoutStereo( Int16 dataInLeft, Int16 dataInRight )
{
while ( !( MCASP1_SRCTL5 & 0x10 ));
MCASP1_XBUF5_32BIT = dataInLeft | 0x00000000; // out the sample to line out and headphone channel left
while ( !( MCASP1_SRCTL5 & 0x10 ));
MCASP1_XBUF5_32BIT = dataInRight | 0x00000000; // out the sample to line out and headphone channel right
return;
}
// ======== WriteDataToLineoutLeft ======================================
// wait for receive ready and copy the sample to left channel using slot 0
void WriteDataToLineoutLeft( Int16 dataInLeft )
{
while ( !( MCASP1_SRCTL5 & 0x10 ));
MCASP1_XBUF5_32BIT = dataInLeft | 0x00000000; // Out the sample to line out and headphone CH2
while ( !( MCASP1_SRCTL5 & 0x10 ));
MCASP1_XBUF5_32BIT = 0x00000000; // // Out a dummy write to line out and headphone CH2
return;
}
// ======== WriteDataToLineoutStereo ======================================
// wait for receive ready and copy the sample to right channel using slot 1
void WriteDataToLineoutRight( Int16 dataInRight )
{
while ( !( MCASP1_SRCTL5 & 0x10 ));
MCASP1_XBUF5_32BIT = 0x00000000; // Out a dummy write to line out and headphone CH2
while ( !( MCASP1_SRCTL5 & 0x10 ));
MCASP1_XBUF5_32BIT = dataInRight | 0x00000000; // out the sample to line out and headphone channel right (CH1 or red wire)
return;
}
// ======== ReadDataFromLinein ==============================================
// wait for receive ready and copy the sample of left channel to the input register
Int16 ReadDataFromLineinLeft( void )
{
Int16 dataInLeft;
while ( ! ( MCASP1_SRCTL0 & 0x20 ) );//&& ! ( MCASP1_RSLOT & 0x01 ) );
if ( ( MCASP1_RSLOT & 0x01 ) == 0 );
dataInLeft = MCASP1_RBUF0_32BIT; // read sample from ADC
return( dataInLeft );
} // don't work at this time !!!!
// ======== ReadDataFromLinein ==============================================
// wait for receive ready and copy the sample of right channel to the input register
Int16 ReadDataFromLineinRight( void )
{
Int16 dataInRight;
while ( ! ( MCASP1_SRCTL0 & 0x20 ) );
if ( ( MCASP1_RSLOT & 0x01 ) == 1 );
dataInRight = MCASP1_RBUF0_32BIT; // read sample from ADC
return( dataInRight );
}
/*----------------------------------------------------------------------------------------- *
* \file fir_basic.c *
* \brief loopback with FIR filtering through the HEADPHONE/LINEOUT jacks *
* ---------------------------------------------------------------------------------------- */
// ======== Includes ========================================================
#include "fir_basic.h"
#include "fir_coefficients.h"
// ======== Globals =========================================================
Int16 x[N]; // Filter input delay line
extern void intcVectorTable( void );
// ======== firInit =========================================================
// initialize to 0 from x(0) to x(n-N) We are fixed to 0 all coefficients of delay line
void firInit( void )
{
Int16 i;
for (i = 0 ; i<N ; i++)
{
x[i] = 0;
}
}
// ======== firFloat ========================================================
float firFloat( float sampleIn )
{
short i;
float sampleOut = 0.0; // Filter output in lineout
x[0] = sampleIn;
for ( i=0 ; i<N ; i++ ) // Calculate output
sampleOut += hlp25[i]*x[i]; // ha is declared and initialized in header file
for ( i=(N-1) ; i>0 ; i-- ) // Shift delay line
x[i] = x[i-1];
return ( sampleOut );
}
// ======== xint0_isr ========================================================
// Interrupt subroutine to calculate the next sample
interrupt void xint0_isr( void )
{
float yn = 0.0; // Filter output in lineout
float xn;
xn = ReadDataFromLineinLeft( ); // Input from ADC
yn = firFloat( xn ); // Calculate the next sample
WriteDataToLineoutStereo( (Int16)(yn), (Int16)(xn) ); // Output to DAC
return;
}
/*------------------------------------------------------------------------ *
* \file main.c *
* \brief implementation of main() *
* ----------------------------------------------------------------------- */
// ======== Includes =======================================================
#include "fir_basic.h"
// ======== main ============================================================
// initialization routines called by example program for interrupt-based i/o
int main( void )
{
/* initialization of I2C module - Set and Enable I2C clock at 20KHz */
printf( "\n" );
printf( "[audio TSK]: initializing I2C module...\n\n" );
EVMOMAPL137_I2C_init( );
/* configuration of codec AIC3106 registers - Default clock is 48KHz */
printf( "[audio TSK]: initializing audio device...\n\n" );
EVMOMAPL137_AIC3106_init( ADC_GAIN_0DB, DAC_ATTEN_0DB, FS_48000_HZ );
printf( "[audio TSK]: setup AIC3106 complete...\n\n" );
/* initialization of McASP - Only McASP1 is use in Spectrum Digital board */
EVMOMAPL137_MCASP_init( FS_48000_HZ );
printf( "[audio TSK]: setup McASP complete...\n\n" );
printf( "[audio TSK]: audio device ready to work...\n\n" );
/* initialization of average coefficients and input buffer */
firInit( );
/* start BSL */
printf( " <-> Release Audio Lowpass FIR Filter --> on HP/Lineout [P12/P13]\n" );
EVMOMAPL137_MCASP_start( );
EVMOMAPL137_MCASP_isr( );
/* loop forever */
while ( 1 );
}