I need to use 32 bit audio signal using I2S slave mode in OMAP-L137 and OMAP-L138.
input Audio Spec : 32 bit , I2S
receive clock : Bit clock, Word clock from other board
I want to get I2S signal and some signal processing and send to other board using I2S signal.
I just copy input buffer to output buffer, but I cannot get I2S signal on the EVM board.
Is there any other setting for pin configuration?
I guess I did not set about PINMUX, I don't know how can I do for PIN configuration.
If my initial file is ok, I can check I2S signal using oscillopscope, but at this time no signal comes out.
Here is my initial file (L137)
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void McASP_Init_L137(void)
{
/* Initialize MCASP1 */
mcasp = &MCASP_MODULE_1;
/* ---------------------------------------------------------------- *
* *
* McASP1 is in Slave mode. *
* BCLK & WCLK come from McASP1 *
* DIN is used by write16/write32 *
* DOUT is usec by read16/read32 *
* *
* ---------------------------------------------------------------- */
mcasp->regs->GBLCTL = 0; // Reset
mcasp->regs->RGBLCTL = 0; // Reset RX
mcasp->regs->XGBLCTL = 0; // Reset TX
mcasp->regs->PWRDEMU = 1; // Free-running
/* RX */
mcasp->regs->RMASK = 0xffffffff; // No padding used
mcasp->regs->RFMT = 0x0001807C; // MSB 16bit, 1-delay, no pad, CFGBus
mcasp->regs->AFSRCTL = 0x00000112; // 2TDM, 1bit Rising, INTERNAL FS, word
mcasp->regs->ACLKRCTL = 0x000000AF; // Rising INTERNAL CLK,(from tx side)
mcasp->regs->AHCLKRCTL = 0x00000000; // INT CLK (from tx side)
mcasp->regs->RTDM = 0x00000003; // Slots 0,1
mcasp->regs->RINTCTL = 0x00000000; // Not used
mcasp->regs->RCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
/* TX */
mcasp->regs->XMASK = 0xffffffff; // No padding used
mcasp->regs->XFMT = 0x0001807C; // MSB 16bit, 1-delay, no pad, CFGBus
mcasp->regs->AFSXCTL = 0x00000112; // 2TDM, 1bit Rising edge INTERNAL FS, word
mcasp->regs->ACLKXCTL = 0x000000AF; // ASYNC, Rising INTERNAL CLK, div-by-16
mcasp->regs->AHCLKXCTL = 0x00000000; // EXT CLK
mcasp->regs->XTDM = 0x00000003; // Slots 0,1
mcasp->regs->XINTCTL = 0x00000000; // Not used
mcasp->regs->XCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
mcasp->regs->SRCTL5 = 0x000D; // MCASP1.AXR1[5] --> DIN
mcasp->regs->SRCTL0 = 0x000E; // MCASP1.AXR1[0] <-- DOUT
mcasp->regs->PFUNC = 0; // All MCASPs
mcasp->regs->PDIR = 0x14000020; // All inputs except AXR0[5], ACLKX1, AFSX1
mcasp->regs->DITCTL = 0x00000000; // Not used
mcasp->regs->DLBCTL = 0x00000000; // Not used
mcasp->regs->AMUTE = 0x00000000; // Not used
{
/* Initialize MCASP1 */
mcasp = &MCASP_MODULE_1;
/* ---------------------------------------------------------------- *
* *
* McASP1 is in Slave mode. *
* BCLK & WCLK come from McASP1 *
* DIN is used by write16/write32 *
* DOUT is usec by read16/read32 *
* *
* ---------------------------------------------------------------- */
mcasp->regs->GBLCTL = 0; // Reset
mcasp->regs->RGBLCTL = 0; // Reset RX
mcasp->regs->XGBLCTL = 0; // Reset TX
mcasp->regs->PWRDEMU = 1; // Free-running
/* RX */
mcasp->regs->RMASK = 0xffffffff; // No padding used
mcasp->regs->RFMT = 0x0001807C; // MSB 16bit, 1-delay, no pad, CFGBus
mcasp->regs->AFSRCTL = 0x00000112; // 2TDM, 1bit Rising, INTERNAL FS, word
mcasp->regs->ACLKRCTL = 0x000000AF; // Rising INTERNAL CLK,(from tx side)
mcasp->regs->AHCLKRCTL = 0x00000000; // INT CLK (from tx side)
mcasp->regs->RTDM = 0x00000003; // Slots 0,1
mcasp->regs->RINTCTL = 0x00000000; // Not used
mcasp->regs->RCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
/* TX */
mcasp->regs->XMASK = 0xffffffff; // No padding used
mcasp->regs->XFMT = 0x0001807C; // MSB 16bit, 1-delay, no pad, CFGBus
mcasp->regs->AFSXCTL = 0x00000112; // 2TDM, 1bit Rising edge INTERNAL FS, word
mcasp->regs->ACLKXCTL = 0x000000AF; // ASYNC, Rising INTERNAL CLK, div-by-16
mcasp->regs->AHCLKXCTL = 0x00000000; // EXT CLK
mcasp->regs->XTDM = 0x00000003; // Slots 0,1
mcasp->regs->XINTCTL = 0x00000000; // Not used
mcasp->regs->XCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
mcasp->regs->SRCTL5 = 0x000D; // MCASP1.AXR1[5] --> DIN
mcasp->regs->SRCTL0 = 0x000E; // MCASP1.AXR1[0] <-- DOUT
mcasp->regs->PFUNC = 0; // All MCASPs
mcasp->regs->PDIR = 0x14000020; // All inputs except AXR0[5], ACLKX1, AFSX1
mcasp->regs->DITCTL = 0x00000000; // Not used
mcasp->regs->DLBCTL = 0x00000000; // Not used
mcasp->regs->AMUTE = 0x00000000; // Not used
}
void McASP_Start_L137(void)
{
/* Starting sections of the McASP*/
mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON; // HS Clk
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON; // HS Clk
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );
mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON; // Clk
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON; // Clk
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );
mcasp->regs->RINTCTL |= RDATA; // enable McASP XMT/RCV interrupts
while ( ( mcasp->regs->RINTCTL & RDATA ) != RDATA );
mcasp->regs->XINTCTL |= XDATA;
while ( ( mcasp->regs->XINTCTL & XDATA ) != XDATA );
mcasp->regs->XSTAT = 0x0000ffff; // Clear all
mcasp->regs->RSTAT = 0x0000ffff; // Clear all
mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON; // Serialize
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON; // Serialize
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );
/* Write a 0, so that no underrun occurs after releasing the state machine */
mcasp->regs->XBUF5 = 0;
mcasp->regs->RBUF0 = 0;
mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON; // State Machine
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON; // State Machine
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );
mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON; // Frame Sync
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON; // Frame Sync
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );
/* Start by sending a dummy write */
while( ! ( mcasp->regs->SRCTL5 & 0x10 ) ); // Check for Tx ready
mcasp->regs->XBUF5 = 0;
{
/* Starting sections of the McASP*/
mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON; // HS Clk
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON; // HS Clk
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );
mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON; // Clk
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON; // Clk
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );
mcasp->regs->RINTCTL |= RDATA; // enable McASP XMT/RCV interrupts
while ( ( mcasp->regs->RINTCTL & RDATA ) != RDATA );
mcasp->regs->XINTCTL |= XDATA;
while ( ( mcasp->regs->XINTCTL & XDATA ) != XDATA );
mcasp->regs->XSTAT = 0x0000ffff; // Clear all
mcasp->regs->RSTAT = 0x0000ffff; // Clear all
mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON; // Serialize
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON; // Serialize
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );
/* Write a 0, so that no underrun occurs after releasing the state machine */
mcasp->regs->XBUF5 = 0;
mcasp->regs->RBUF0 = 0;
mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON; // State Machine
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON; // State Machine
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );
mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON; // Frame Sync
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON; // Frame Sync
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );
/* Start by sending a dummy write */
while( ! ( mcasp->regs->SRCTL5 & 0x10 ) ); // Check for Tx ready
mcasp->regs->XBUF5 = 0;
}
Thanks in advance
Doug