I am using OMAP-L138 C6000 DSP+ARM processor. I have some code for power management that puts to sleep the external RAM (DDR) when CPU is idle and wakes it up when something needs to run again. The code is identical on DSP and ARM side and whoever goes to sleep last disables the DDR and whoever wakes up first enables it back again.
Disable and enable DDR here means simply trying to follow instructions for DDR power management as specified in Technical Reference Manual (spruh77a section 15.2.16.1 for DDR Power Management). This involves putting DDR in self refresh and then disabling the clocks (enable self refresh mode, then stop MCLK, wait 150 CPU cycles, disable the DDR through PSC, and then disable PLL/PLLC1). When coming back up its the reverse and the process being followed is as described in the datasheet that I just referenced. DSP though does not seem to like resetting of Memory Controller post enable of DDR from the Power and Sleep Controller registers. The exact bit is following:
"Set the RESET_PHY bit in the DDR PHY reset control register (DRPYRCR) to 1. This resets the
DDR2/mDDR memory controller PHY. This bit will self-clear to 0 when reset is complete."
As soon as I add code in DSP to do the above it starts crashing after 7-8 sleep and wake cycles. If I remove this then it seems to last considerably longer but it falls apart later due to DDR corruption. ARM has the same code and it manages to do this without any issues. I think that resetting of controller post clock enable is required so probably I cant just skip this step and this could be the cause of the DDR corruption that I see if I am not doing it. So is there anything I can check on DSP side?
I am using SYSBIOS idle loop to disable the memory on DSP. This gets re-enabled via a Hwi hook. Any help would be greatly appreciated and do let me know if any more information is needed.