AISgen "Use direct clock from PLL1"

Hi, everyone,

I have a problem of the initialization of DDR memory in the following environment.

Processor : OMAP L-138 and AM1806

Memory : DDR2

Boot mode : SPI0

PLL0 Settings : CPU(372 MHz) Pre-Divisor=2, Multiplier=31, Post-Divisor=1, DIV1=1, DIV3=16, DIV7=8

PLL1 Settings : DDR(312MHz) Multiplier=13, Post-Divisor=1, DIV1=1, DIV2=2, DIV3=3

DDR memory is driven  with 156MHz.

There is a check-box "Use direct clock from PLL1" in the DDR setting tab.

If I check it , our board failed to boot once time in 300 times.

If I don't check it, our board never fail.

But the 2X_CLK should be same to DDR memory because PLL1 Post-Divisor is 1.

(1)What register is changed by "Use direct clock from PLL1"  check box.

(2)This option can be used ?

Thank you for your help!!!