Hello,
I'd like to know the details about timing behavior for recieving data on AM180x UART module because our system is like noisy condition. My understanding is below. Is it correct? Please give me some advice.
BCLK has been driving and RX data is high level. Then RX data is changed state from high to low. The falling edge of BCLK which is immediately after changing state of RX detects low level. This BCLK cycle is the 1st for sampling. If RX data at falling edge of the 8th BCLK is low, the module detects a start bit (MDR.OSM_ SEL==0, 16x mode). If RX data from the 1st to the 15th BCLK are low, but RX data at the 16th BCLK is high, the module can recognize a start bit correctly, can't it? The D0 bit which is next a start bit is sampled at falling edge of the 24th BCLK? (24=16+8 in 16x mode)
Regards,
Kazu