Hi Friends,
I got an interesting problem & was unable to correlate different observations i found on debug. Requesting experts help.
#1 Intentional HW reset OR on system reset from Debug mode of CCS makes L138 DDR2 boot works perfect and not required on L138 IRAM Boot
First I thought Booting is not happening at all while using DDR2 for Boot sequence, but the init is going well and the PC is switched to entry point and executed further. From this state I tried to find the point where code halts by loading code symbol, and found debug pointer is moving in weird manner while single stepping (not in a sequential manner as i written in my code). But on L138 IRAM Boot all test above are giving desired outputs.
About this observation, I was not able find any conclusion and also unable to find relation of RESET & L138 DDR2 Boot which is not applicable on L138 IRAM Boot. I am using same board (custom board designed for a product) for all above mentioned test). Some timing are there in this case?
#2 [suspect] using Cache L1p/L1d & L2, but initializing cache in my code.
_entry_point >> PMIC Vge change to 1.3v for 456mHz operation support(i2c Init for PMIC interface) >> PSC wake up >> UART init >> Cache >> to scheduler loop
Here we are enabling cache on DDR, while the same .text section is residing in the DDR area where cache is enabling. Is this will create any problem? But we tried this code with JTAG and didn’t found any issues.
[ if statement 3 is a problem, I don’t find links to connect with statement 2 ]
#3 [Related issue] when we moved entire code to DDR2, debugging using XDS510 is showing some problem but with XDS560 it is perfectly working
Debbugging code on DDR location using XDS510 shows pointer jumping weird on step in from CCS Debug, but with XDS560 it works perfectly. Again I was not able to relate code running on DDR and JTAG debug
All these issues starts at my end after i added a compression library which created hole on .text and it not even fits to the full IRAM size. So i decided to move to DDR2. I have not using any CCS optimization in my code but relay on cache for equivalent performance as it is running on IRAM and i had appreciable result on debugging and testing. But these 4 issues arises after we tried to boot the entire code on platform.
Request suitable help from all.
Thank You,
Regards
Shino Samuel, C-DAC (T)