Hello!
We have used four memory bus masters: EDMA0_0 for McBSP (permanent), EDMA0_1 for SPI (frequent-periodic), EDMA1 for manual periodic big data block transfers, and also there is DSP.
There is a problem: on some pick loads EDMA0_1 is not in time to fill in SPI TX. As far as we see, memory bus is overloaded with accesses and EDMA TRs encounters delays from time to time.
Solution can be: "pause" EDMA1 transfers while SPI communication is performing (SS asserted): this timing is not critical for EDMA1 transfers.
But here is a problem too: EDMA1 holds not one, but few transfers, some of them are consecutive, some intended to be "parallel", some are a bit complicated executing sorting, and actually a full power of linking and chaining is used. So manual implementation of "EDMA scheduler" still is possible, but is very complicated.
Question: maybe there is an easy way/trick to just "pause" EDMA CC/TC and then "resume" so it just continues with it's previous job (although I don't see this is TRM)? Because, as I understand, if just disable channel in the middle of the transfer, and then enable with pushing manual start again - this will not work, or at least we're risking to lose some events. And anyway whole EDMA1 at one pausing is preferable.