Hello,
regarding the "System-Level ESD Immunity Usage Note" in the errata sheet (sprz301h.pdf chapter 2.1.4) we disabled the DLL REFCLK signal by setting undocumented bit 13 in DDRPHYCTL1. In addition we changed the clock to the mDDR to 150 MHz (sprs586d.pdf chapter 2.1 Device Characteristics).
Now on some devices a few bits in the RAM toggle without influence of the application.
When I go back to 133 MHz the RAM content is stable - when I ignore the errata (i.e. not disabling DLL REFCLK), the RAM content also is stable.
we use:
OMAP-L138 Rev. 2.1
mDDR: Mobile LPDDR MT46H16M16LFBF-5 IT with max. Clock-Rate: 200 MHz
Why is there an influence of the DLL REFCLK status with the RAM stability?
Best regards
Martin