Hi,
One of my customer has a trouble with ESD issue in OMAPL138 system.
To be robust to ESD strike in OMAPL138 system, it is recommended to use an external 3.3V clock source with a resistor voltage divider, but actually they are using an internal oscillator.
Now some possible workarounds can be found in the eratta as below:
======================
• The OSCIN and OSCVSS (and OSCOUT, if used) should be routed as short as possible to reduce
their ability to pick up EMI noise.
• Route the OSCIN signal on inner board layers where it is shield by power and ground planes.
• Disable the DLL REFCLK signal in the DDR EMIF PHY. This prevents the DLL used by the DDR PHY
from dynamically tracking glitches on the input clock. This can be done after normal DDR initialization
by setting the following bit in the DDR PHY Control Register (0xB00000E4):
// Configure DDR PLL
Set_DDRPLL_150MHz();
// Configure DDR timings
DEVICE_DDR2Config(150);
// Minimum 600 MCLK cycle delay (allow master DLL to lock)
Delay_600();
// Perform dummy DDR read
volatile unsigned int k=0;
...
k = *(volatile unsigned int*) (0xC0000000);
// Disable DLL REFCLK
DRPYC1R |= 0x00002000;
• The processor should be provided as much power supply decoupling as is practical and placed as
close to the processor as possible.
• Follow the entire DDR interface implementation requirements in the device datasheet.
• Implement the PLL filtering circuits shown in the device datasheet.
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It looks a possible workaround (DDR initialization described in the above) can be applied without HW changes.
Do you have any other ideas for workaround without HW changes ?
Also, it is appreciated if you could suggest some experiences to be robust ESD strike with *minimal* HW (PCB) changes.
Best Regards,
Kawada