I have write a project, it is used well in simulation?
when I make the project start from flash, it does not work.
The cmd file is:
-l rts67plus.lib
-stack 0x00000800
-heap 0x00000800
MEMORY
{
dsp_l2_ram: ORIGIN = 0x11800000 LENGTH = 0x00040000
dsp_l1_pram: ORIGIN = 0x11e00000 LENGTH = 0x00008000
dsp_l1_dram: ORIGIN = 0x11f00000 LENGTH = 0x00008000
entry_point: ORIGIN = 0x80010000 LENGTH = 0x00000080
shared_ram: ORIGIN = 0x80010080 LENGTH = 0x00007F80
external_ram: ORIGIN = 0xC3000000 LENGTH = 0x01000000
}
SECTIONS
{
.text:_c_int00 > entry_point
.cinit > dsp_l2_ram
.text > dsp_l2_ram
.const > dsp_l2_ram
.bss > dsp_l2_ram
.far > dsp_l2_ram
.switch > dsp_l2_ram
.stack > dsp_l2_ram
.data > dsp_l2_ram
.sysmem > dsp_l2_ram
.cio > dsp_l2_ram
}
when I change it as follow:
-l rts67plus.lib
-stack 0x00000800
-heap 0x00000800
MEMORY
{
dsp_l2_ram: ORIGIN = 0x11800000 LENGTH = 0x00040000
dsp_l1_pram: ORIGIN = 0x11e00000 LENGTH = 0x00008000
dsp_l1_dram: ORIGIN = 0x11f00000 LENGTH = 0x00008000
entry_point: ORIGIN = 0x80010000 LENGTH = 0x00000080
shared_ram: ORIGIN = 0x80010080 LENGTH = 0x00007F80
external_ram: ORIGIN = 0xC3000000 LENGTH = 0x01000000
}
SECTIONS
{
.text:_c_int00 > entry_point
.cinit > external_ram
.text > external_ram
.const > external_ram
.bss > external_ram
.far > external_ram
.switch > external_ram
.stack > external_ram
.data > external_ram
.sysmem > external_ram
.cio > external_ram
}
How can I use the L1 and L2 RAM?
How can I make all the section in the internal RAM?
what is the meaning of every section such as cinit?