Hello!
I'm having some trouble starting the MCASP ACLKX on the OMAP-L138. My goal is to use the AHCLKX with a divide-by-1 and output the serial clock to the other devices in the system. From the data sheet, the serial clock would be a direct feed-through of the AHCLKX input signal.
With just the DSP in the circuit, I can configure everything the way that I would like, except changing the AHCLKRCTL register to 0x00000000 - this is to change the HCLKXM bit from 1(default) to 0, telling the ACLKX to use the AHCLKX input as the source to perform the clock divide on.
If I leave HCLKXM as a 0, everything seems to work fine. The serial clock runs, a signal appears on the output pin and I can adjust the divide ratio as I please, the only problem is that this passes the system clock through which is not of a desirable frequency.
The main problem that I feel I am having is getting the serial clock to release from reset after switching the HCLKXM source (the GBLCTL write/read hangs). It seems like the AHCLKX input pin should just be passed through when the clock is in reset, but as soon as that bit is changed, the output pin is held high and stays that way. My understanding is that nothing in the GBLCTL can be latched without a serial clock...but my serial clock seems to be completely stopping.
In spruh77a_omap.pdf, table 25-10 says that there is a restriction on changing HCLKXM, am I missing something here?
Do I have to run through the configuration/initialization once and then adjust with a second pass?
Is there a special reset order that has to be followed when using the mcasp in mixed clock mode?
Could the Mux that switches based on HCLKXM be shot?
Any thoughts would be greatly appreciated.