CCS/66AK2G12: About DDR3 access way

Dear Rahul,

Currently, we are developing products using 66AK2G12.

Debug DSP and ARM via Jtag using CCS, but there are some issues. Please let us know what you think.

The problems are as follows.
When the main program starts from DDR3 (using Jtag), we can write correct value to DDR3.
When the main program is started from other (cache or shared memory),

we can write to DDR3, but the value is not correct value.
we asked to below URL. Are there related?
e2e.ti.com/.../848220

Best regards