AM3351: DDR2 signal integrity and timing not according to JEDEC compliance measurements

Part Number: AM3351

Hi!

It has been a while on the DDR2 topic, before our equipment was not good and also time was limited to analyze in-depth, but lately we have had time to measure integrity and timing of the DDR2. The previous question about the Vswing is not applicable anymore, we solved the amplitude with an parallel termination on the clock differential and series termination. (Not sure why this is not added in the datasheet as a requirement on the differential clock to the DDR2 device.)

Now we almost finalized the qualification successfully but we run into a few points which are not okay yet. (Below the measurement I'll share details about the design).

1.  When measuring read bursts timing fails on:

- tAC-Diff, CK, DQ which is required to be +/- 500 ps. Measurement results show between -628.75 ps and -282.71 ps.

Where the signals are (all measured close to the CPU):

- C1 -> CK_p/n

- C2 -> DQS1_p/n

- C3 -> DQ8

2. Second measurement on read burst where timing fails:

- tDQSQ-Diff, DQ, DQS which is required to be less than +300ps. Measurement results show +396.45ps (with an average of 288.93ps and a low of -387.77ps).

Signals are same as the previous measurement.

3. The third measurement is an signal integrity measurement where we do not meet the JEDEC:

- Vox(ac)DQS, DQS, DQS# where the low limit is 775mV and high limit 1.025V. From the measurement result we see the low limit is not met and results in 421.89mV.

As shown in the histogram we do not meet this JEDEC spec.

Can you advice on these measurements and fails?

The design consist of a DDR2 (ISSI) device (IS43DR16640C-25DBLI) connected to the CPU (AM3351).

The DDR2 settings in the Sitara CPU are as follow:

arch/arm/include/asm/arch-am33xx/ddr_defs.h:28:#define IS43DR16640C25DBLI_EMIF_READ_LATENCY   0x100306
arch/arm/include/asm/arch-am33xx/ddr_defs.h:29:#define IS43DR16640C25DBLI_EMIF_SDCFG                   0x43845732
arch/arm/include/asm/arch-am33xx/ddr_defs.h:30:#define IS43DR16640C25DBLI_EMIF_SDREF                   0x2000040d
arch/arm/include/asm/arch-am33xx/ddr_defs.h:31:#define IS43DR16640C25DBLI_EMIF_TIM1                       0x0666a392
arch/arm/include/asm/arch-am33xx/ddr_defs.h:32:#define IS43DR16640C25DBLI_EMIF_TIM2                       0x142431ca
arch/arm/include/asm/arch-am33xx/ddr_defs.h:33:#define IS43DR16640C25DBLI_EMIF_TIM3                       0x0000021f
arch/arm/include/asm/arch-am33xx/ddr_defs.h:34:#define IS43DR16640C25DBLI_INVERT_CLKOUT            0x0
arch/arm/include/asm/arch-am33xx/ddr_defs.h:35:#define IS43DR16640C25DBLI_IOCTRL_VALUE               0x373
arch/arm/include/asm/arch-am33xx/ddr_defs.h:36:#define IS43DR16640C25DBLI_PHY_FIFO_WE                0x5d
arch/arm/include/asm/arch-am33xx/ddr_defs.h:37:#define IS43DR16640C25DBLI_PHY_WR_DATA               0x40
arch/arm/include/asm/arch-am33xx/ddr_defs.h:38:#define IS43DR16640C25DBLI_RATIO                              0x80
arch/arm/include/asm/arch-am33xx/ddr_defs.h:39:#define IS43DR16640C25DBLI_RD_DQS                          0x40
arch/arm/include/asm/arch-am33xx/ddr_defs.h:40:#define IS43DR16640C25DBLI_WR_DQS                         0x6

PCB trace lengths between CPU (U2000) and DDR2 (U4001) are as follow:

Thank you in advance!

Francois.