L138 EDMA3 Linked transfers PaRAM change latency

Hello,

I'm currently using the EDMA3 controller on the OMAP L138 for 16-bit transfers to and from the SPI0 peripheral. The SPI0 peripheral is set up as a slave and is being driving at almost 25MHz (so about 750 ns per 16-bit transfer). The DMA transfer in is set up as a ping-pong buffer (using PaRAM set 14 and set 64 and 65 for reload for ping and pong).

Initiate streaming to memory works fine (mDDR in this case), but the DMA engine seems to lose a sample when updating the PaRAM 14 set with either set 64 or 65. 

I'll up the clock speed (I'm not currently running full speed) and switch to ping-pong memory in L2 to see if things improve, but it would be useful to understand what the latency is for the reloading of the PaRAM set in terms of clock cycles.

Thanks