Hi,
We have few questions regarding DDR2 and AM1808.
I am sorry if these are repeated questions.
Our customer is using DDR2 with AM1808 and few of the custom
boards has system crash issue related to DDR2.(confirmed with a test program)
note:The DDR is configured in point-to-point, without any external termination.
The drive strength is set to weak as per the datasheet guideline.
Meanwhile we have few test results about the DDR2 behaviour as below.
Please let me know if there are any known reasons or general comments on this.
1.Before the System crash, the DDR memory seems fine but after the crash
the memory is unstable with constantly changing bits.
They see the data on the DDR changing constantly even when
the CPU and all clocks are OFF. But restores with a reset on DDR PHY.
Debugger is accessing memory directly through debug core.
MPU is in "abort" mode, and stuck in exception vector(s).
Usually the exception vectors 0xc, 0x10, 0x14.
2.After the crash, normal memory behavior can be recovered by resetting
DDR2 controller using DRPYRCR register. Bits are stable, and original,
uncorrupted memory reappears.
3.It seems all the custom board units show this exact behavior if they add 2.2pF
capacitance on DQS1 signal line. This is extremely low value, and should be
no problem. Simulations show S.I.is also well within spec even with 2.2pF.
A small bump is seen on the rising edge of DQS1 with increased capacitance.
4.Using full drive strength of DDR2 memory this bump "disappears" (due
to overshoot), and all units become stable, and can tolerate up to 4pF added load.
5.As mentioned in the AM1808 datasheet, the parallel termination is not allowed,
but the signal integrity improves with the parallel termination(based on the
simulation). What is the reason TI does not allow parallel termination.
Above observations indicates that the MPU DDR2 controller reaches some
kind of unstable state, which is recovered when the DDR2 PHY is reset.
Best Regards
Prad.