uPP DMA EOLI to late

I use the OMAP-L138 and an ADS8558.
They are linked through the uPP.
On GPIO bank 6 I generate the CONVST, CS, RD (ADS) and ENABLE, CLOCK (uPP) signals.
The uPP-STARTA Signal is disabled (UPICR).
CS, RD and CLOCK are driven by one GPIO together.


The dma-descriptor is configured to get 6 words:

    if (!CSL_FEXT(upp0Regs->UPIS2, UPP_UPIS2_PEND)
            && !CSL_FEXT(upp0Regs->UPIS2, UPP_UPIS2_ACT))
        upp0Regs->UPID0 = (uint32_t) &uppInputBuffer;
        upp0Regs->UPID1 = CSL_FMK(UPP_UPID1_LNCNT, 1)
                | CSL_FMK(UPP_UPID1_BCNTH, 6);
        upp0Regs->UPID2 = (0);
    }


But the following loop exits after 11 cycles:

    // CLK/RD until EOLI/EOWI/ERROR:
    while (upp0Regs->UPIER == 0) {
        // CLK/CS/RD low:
        *gpio_bank6_out_data = gpio_b6_state[state_ADS_CONVST_H_ADS_CS_L_UPP_EN_L];
        // CLK/CS/RD high:
        *gpio_bank6_out_data = gpio_b6_state[state_ADS_CONVST_H_ADS_CS_H_UPP_EN_L];
    }

In uppInputBuffer[0]..[5] are the datas, uppInputBuffer[6] is untouched, but the datas are at wrong order:
I have to reorder it whith this statement:

    inputData[0] = uppInputBuffer[4]);
    inputData[1] = uppInputBuffer[5]);
    inputData[2] = uppInputBuffer[0]);
    inputData[3] = uppInputBuffer[1]);
    inputData[4] = uppInputBuffer[2]);
    inputData[5] = uppInputBuffer[3]);

My questions:
1.) Why it takes 11 clocks?
2.) Why it is in wrong order?

Can help somebody?

Andreas

--
PS. uPP conf:

    // uPP Channel Control Register
    upp0Regs->UPCTL = CSL_FMKT(UPP_UPCTL_MODE, RECEIVE)
            | CSL_FMKT(UPP_UPCTL_CHN, ONE)
            | CSL_FMKT(UPP_UPCTL_SDRTXIL, DISABLE)
            | CSL_FMKT(UPP_UPCTL_DDRDEMUX, DISABLE)
            | CSL_FMKT(UPP_UPCTL_DRA, SINGLE) | CSL_FMKT(UPP_UPCTL_IWA, 16BIT)
            | CSL_FMKT(UPP_UPCTL_DPWA,FULL);

    // uPP Interface Configuration Register
    upp0Regs->UPICR = CSL_FMKT(UPP_UPICR_STARTA, DISABLE)
    | CSL_FMKT(UPP_UPICR_ENAPOLA, INVERT) | CSL_FMKT(UPP_UPICR_ENAA, ENABLE)
            | CSL_FMKT(UPP_UPICR_CLKINVA, NORMAL)
            | CSL_FMKT(UPP_UPICR_STARTPOLA, INVERT);

    // idle value register
    upp0Regs->UPIVR = CSL_FMKT(UPP_UPIVR_VALA, RESETVAL);

    // uPP Threshold Configuration Register
    upp0Regs->UPTCR = CSL_FMKT(UPP_UPTCR_RDSIZEI, 64B);

    // uPP Interrupt Enable Set Register
    upp0Regs->UPIES = CSL_FMKT(UPP_UPIES_EOLI, SET)
            | CSL_FMKT(UPP_UPIES_EOWI, SET);

    // DLB:
    CSL_FINST(upp0Regs->UPDLB, UPP_UPDLB_BA, DISABLE);
    CSL_FINST(upp0Regs->UPDLB, UPP_UPDLB_AB, DISABLE);

    // uPP Peripheral Control Register
    CSL_FINST(upp0Regs->UPPCR, UPP_UPPCR_EN, ENABLE);