Hi,
I will use the TM64P3_Out12 Event to enable a AB-synchronized EDMA transfer. CCNT is 3.
Is the TEVT12 always set when an interrupt is set or do I have to enable more than only the PRDINTEN12?
I know that I have to clear the Interrupt flag when one occured, do I have to do the same with the EDMA3 event flag if this is accessable from "outside" or is it automatically reseted after the event is submitted to the EDMA3 CC?
I have the TM64P3_Out12 also available on a GPIO to trigger a AD conversion on the EMIFA connected ADCs. At the same time, the EDMA3 system shall transfer the last ADC values from the ADCs to an other memory section. Thus, the EDMA3 CC shall react also on this EVANT. I see on a connected Oszilloscope that the puls of the timer occurs as expected, but no change in the EDMACC1 IPR can observed. The CCNT is 4, I hope that means that 4 transfers must be triggerd before the bit in the IPR is set? The bit is never set... The corresponding EVENT is 26, am I right? I configured the the EDMACC and PaRAM-sets (Set26 links to Set 127. Set127 links back to 26) as followed:
/*
* Setup the EDMA3 CC1
*/
/*Enable Event 26 in EDMA3CC1. Event 26 comes from TM64P3_Out12*/
CSL_FINST(Edma31cc0Regs->EESR, EDMA3CC_EESR_E26, SET);
/*Map Event 26 on EDMACC1 to Queue Q0 - should be by default but only to be safe*/
CSL_FINST(Edma31cc0Regs->DMAQNUM[3], EDMA3CC_DMAQNUM_E2, Q0);
/* Enable EDMA3CC1 Interrupt 0 - Ping Buffer - This interrupt needs to be served by the TCC in PaRAM.OPT */
CSL_FINST(Edma31cc0Regs->IESR, EDMA3CC_IESR_I0, SET);
/* Enable EDMA3CC1 Interrupt 1 - Pong Buffer - This interrupt needs to be served by the TCC in PaRAM.OPT */
CSL_FINST(Edma31cc0Regs->IESR, EDMA3CC_IESR_I1, SET);
/*
* relative Memory-Addresses of PaRAM sets
* PaRAM set 26: 0x4340 (responsible for EVENT26 (Timer64P3 Out12))
* PaRAM set 127: 0x4FE0
*/
/*
* PaRAM set 26 for PING buffer - 16 bit
*/
/* Intermediate transfer completion chaining disable */
CSL_FINST(Edma31cc0Regs->PARAMSET[26].OPT, EDMA3CC_OPT_ITCCHEN, DISABLE);
/* Transfer complete chaining disable */
CSL_FINST(Edma31cc0Regs->PARAMSET[26].OPT, EDMA3CC_OPT_TCCHEN, DISABLE);
/* Intermediate transfer completion interrupt disable */
CSL_FINST(Edma31cc0Regs->PARAMSET[26].OPT, EDMA3CC_OPT_ITCINTEN, DISABLE);
/* Transfer complete interrupt enable */
CSL_FINST(Edma31cc0Regs->PARAMSET[26].OPT, EDMA3CC_OPT_TCINTEN, ENABLE);
/* TCC is 0 to set after transfer completion the bit 0 in IPR */
CSL_FINS(Edma31cc0Regs->PARAMSET[26].OPT, EDMA3CC_OPT_TCC, 0);
/* Transfer completion mode */
CSL_FINST(Edma31cc0Regs->PARAMSET[26].OPT, EDMA3CC_OPT_TCCMOD, NORMAL);
/* FIFO width */
/* Applies if either SAM or DAM is set to constant addressing mode.
* SAM or DAM isn't supported at any controller on OMAPL138, therefore dosen't matter which size is choosen */
CSL_FINST(Edma31cc0Regs->PARAMSET[26].OPT, EDMA3CC_OPT_FWID, 256BIT);
/* Updating PaRAM-set after TR submitted */
CSL_FINST(Edma31cc0Regs->PARAMSET[26].OPT, EDMA3CC_OPT_STATIC, NORMAL);
/* AB-synchronized transfer ACNT and BCNT */
CSL_FINST(Edma31cc0Regs->PARAMSET[26].OPT, EDMA3CC_OPT_SYNCDIM, ABSYNC);
/* Increment Destination Adress */
CSL_FINST(Edma31cc0Regs->PARAMSET[26].OPT, EDMA3CC_OPT_DAM, INCR);
/* Increment Source Adress - Constant would be the better choice in this case but isn't supported by L138 */
CSL_FINST(Edma31cc0Regs->PARAMSET[26].OPT, EDMA3CC_OPT_SAM, INCR);
/* Source Address of the Ping buffer -> Start Address of EMIFA connected ADCs */
CSL_FINS(Edma31cc0Regs->PARAMSET[26].SRC, EDMA3CC_SRC_SRC, 0x66000001);
/* Number of bytes in an Array */
CSL_FINS(Edma31cc0Regs->PARAMSET[26].A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 0x0002);
/* Number of Arrays per transfer (Frame) */
CSL_FINS(Edma31cc0Regs->PARAMSET[26].A_B_CNT, EDMA3CC_A_B_CNT_BCNT, 0x0002);
/*Start address of destination */
CSL_FINS(Edma31cc0Regs->PARAMSET[26].DST, EDMA3CC_DST_DST, BuffAddressPing);
/*modification of destination address after transfer one array */
CSL_FINS(Edma31cc0Regs->PARAMSET[26].SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_DSTBIDX, 0x0003);
/*modification of source address after transfer one array. must be zero, the ADCs are always connected to the same address */
CSL_FINS(Edma31cc0Regs->PARAMSET[26].SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0x0000);
/*Link to PaRAM-set 127 at Address 0x4FE0 */
CSL_FINS(Edma31cc0Regs->PARAMSET[26].LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_LINK, 0x4FE0);
/*Modification of destination address in 3rd dimension (CCNT...) */
CSL_FINS(Edma31cc0Regs->PARAMSET[26].SRC_DST_CIDX, EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0x0000);
/*Modification of source address in 3rd dimension (CCNT...) */
CSL_FINS(Edma31cc0Regs->PARAMSET[26].SRC_DST_CIDX, EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0x0000);
/*CCNT */
CSL_FINS(Edma31cc0Regs->PARAMSET[26].CCNT, EDMA3CC_CCNT_CCNT, 0x0004);
/*
* PaRAM set 127 for PONG buffer - 16 bit
*/
/* Intermediate transfer completion chaining disable */
CSL_FINST(Edma31cc0Regs->PARAMSET[127].OPT, EDMA3CC_OPT_ITCCHEN, DISABLE);
/* Transfer complete chaining disable */
CSL_FINST(Edma31cc0Regs->PARAMSET[127].OPT, EDMA3CC_OPT_TCCHEN, DISABLE);
/* Intermediate transfer completion interrupt disable */
CSL_FINST(Edma31cc0Regs->PARAMSET[127].OPT, EDMA3CC_OPT_ITCINTEN, DISABLE);
/* Transfer complete interrupt enable */
CSL_FINST(Edma31cc0Regs->PARAMSET[127].OPT, EDMA3CC_OPT_TCINTEN, ENABLE);
/* TCC is 1 to set after transfer completion the bit 1 in IPR */
CSL_FINS(Edma31cc0Regs->PARAMSET[127].OPT, EDMA3CC_OPT_TCC, 1);
/* Transfer completion mode */
CSL_FINST(Edma31cc0Regs->PARAMSET[127].OPT, EDMA3CC_OPT_TCCMOD, NORMAL);
/* FIFO width */
/* Applies if either SAM or DAM is set to constant addressing mode.
* SAM or DAM isn't supported at any controller on OMAPL138, therefore dosen't matter which size is choosen */
CSL_FINST(Edma31cc0Regs->PARAMSET[127].OPT, EDMA3CC_OPT_FWID, 256BIT);
/* Updating PaRAM-set after TR submitted */
CSL_FINST(Edma31cc0Regs->PARAMSET[127].OPT, EDMA3CC_OPT_STATIC, NORMAL);
/* AB-synchronized transfer ACNT and BCNT */
CSL_FINST(Edma31cc0Regs->PARAMSET[127].OPT, EDMA3CC_OPT_SYNCDIM, ABSYNC);
/* Increment Destination Adress */
CSL_FINST(Edma31cc0Regs->PARAMSET[127].OPT, EDMA3CC_OPT_DAM, INCR);
/* Increment Source Adress - Constant would be the better choice in this case but isn't supported by L138 */
CSL_FINST(Edma31cc0Regs->PARAMSET[127].OPT, EDMA3CC_OPT_SAM, INCR);
/* Source Address of the Ping buffer -> Start Address of EMIFA connected ADCs */
CSL_FINS(Edma31cc0Regs->PARAMSET[127].SRC, EDMA3CC_SRC_SRC, 0x66000001);
/* Number of bytes in an Array */
CSL_FINS(Edma31cc0Regs->PARAMSET[127].A_B_CNT, EDMA3CC_A_B_CNT_ACNT, 0x0002);
/* Number of Arrays per transfer (Frame) */
CSL_FINS(Edma31cc0Regs->PARAMSET[127].A_B_CNT, EDMA3CC_A_B_CNT_BCNT, 0x0002);
/*Start address of destination */
CSL_FINS(Edma31cc0Regs->PARAMSET[127].DST, EDMA3CC_DST_DST, BuffAddressPong);
/*modification of destination address after transfer one array */
CSL_FINS(Edma31cc0Regs->PARAMSET[127].SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_DSTBIDX, 0x0003);
/*modification of source address after transfer one array. must be zero, the ADCs are always connected to the same address */
CSL_FINS(Edma31cc0Regs->PARAMSET[127].SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0x0000);
/*Link to PaRAM-set 26 at Address 0x4340 */
CSL_FINS(Edma31cc0Regs->PARAMSET[127].LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_LINK, 0x4340);
/*Modification of destination address in 3rd dimension (CCNT...) */
CSL_FINS(Edma31cc0Regs->PARAMSET[127].SRC_DST_CIDX, EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0x0000);
/*Modification of source address in 3rd dimension (CCNT...) */
CSL_FINS(Edma31cc0Regs->PARAMSET[127].SRC_DST_CIDX, EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0x0000);
/*CCNT */
CSL_FINS(Edma31cc0Regs->PARAMSET[127].CCNT, EDMA3CC_CCNT_CCNT, 0x0004);
Is there anything wrong configured in the program above?
Is there a special configuration on the Timer registers needed to submitt the event to EDMA3 CC?
thanks,
Christian