I'm using a 6748 EMIF interfaced to an FPGA via chip select CS3
The TI docs in one place suggest the Turnaround Time feature (values set in bits 3:2 of register CE3CFG) exists to prevent data bus contention with memory devices that are slow to release the bus (implying turnaround inserts a delay between a read followed by a write.
Other parts of the doc describe this in terms of inserting delay between a write followed by a read.
It makes sense to have both.
1) Can someone confirm that is the actual behavior?
(Sorry, I don't have a dev board or a simulation model yet.)
TI's timing diagrams show the deassertion of signals at the end of an async EMIF read and write transaction, but do not show or explicitly describe the behavior when two consecutive accesses of the same type are performed (2 or more consecutive reads, or 2+ consecutive writes).
The docs DO say there is no turnaround cycle inserted when resuming a transfer to the same location (e.g., the second byte transfer in 8-bit mode of a 16-bit quantity).
The docs also say there is no turnaround cycle inserted between two transfers of the same direction within the same chip-select.
But since the CE3CFG[TA] bits = One less than the actual number of cycles inserted, this suggests one turnaround cycle is ALWAYS inserted, or at least when a turnaround cycle is appropriate.
So I'm not completely clear:
2a) Is there ALWAYS one turnaround cycle inserted between EVERY access?
2b) When doing 2 consecutive reads or 2 consecutive writes within the same CS3 and TA=0, will CS3 be deasserted for at least one clock cycles between operations? Or is it possible to have CS3 asserted for as long as consecutive operations in the same direction are ongoing?
Thanks again.
:)