Using a 6748, with EMIF CS3 to access my FPGA's register bank
It appears CS0 is intended for synchronous use with SDRAM, while CS[2:5] are intended for interfacing to async devices.
But from first looks at the data sheet timing, it appears I could use the EMA_CLK as a clock to my FPGA (selected by CS3) and treat it as a fully synchronous interface (like a clocked SRAM).
Is there any reason I couldn't do this?
The async interface options are to either sample the EMIF Addr, Data, OE, WE, etc... on my FPGA core clock (no relation to EMIF clock), and include the appropriate metastability-minimizing synchronization registers, or use the edges of OE and WE as clocks at that interface.
I realize all 3 approaches require metastability-handling registers when crossing over into my FPGA core clock domain; don't worry, they will be there. :)
I just prefer first approach (all synchronous) if possible, where the boundary crossings can happen in something like a FIFO that doesn't generate a bunch of setup/hold warnings in my VHDL/Verilog simulations.
Many thanks!