Hi,
Please tell us about the timing of the frame interrupt C6748 VPIF module.
There is a description of the two following 34.2.12.2.1 Interrupt Condition Technical Reference Manual (SPRUH79A).
(1) The VPIF generates the following events as conditions for interrupt assertion:
In normal YC receive / transmit mode, EAV on line L1 (and EAV on line L7 in field interrupt for bottom field). Both L1 and L7 are described in Figure 34-4 and Figure 34-5.
(2) The interrupt signal from the VPIF is asserted when the vertical synchronization signal is received.
In the case of (1), Frame interrupt occurs at the timing of the L1 or L7
In the case of (2), When it receives a vertical sync signal, and generating an interrupt
It has been interpreted as, but either (1) and (2) is correct?
Best Regards,
hamada