Hello, everyone who see this post.
Thanks for your interest.
I'm working with OMAP-L138 SOM-M1(TMS320C6748) made by Logic PD and AK4646(CODEC, AKM).
I have a question about McASP0.
This is the detail.
I'm using receive function and transmit function by I2S of TDM. So, the slots that I use are two. The problem is on the side of receiving. I don't use DMA nor FIFO. I get the data from RBUF through the Peripheral configuration bus.
I want to take only Rch to receive. So, I get a data two times from RBUF15 to a variables(dataIn16_0, dataIn16_1) in ISR(interrupt service routine by RDATA interrupt working with sys/bios).
For example
ISR{
dataIn16_0 = RBUF15
dataIn16_1 = RBUF15
:
:
}
I think that the first for Lch(odd slot) and the second Rch(even slot) are sequential.
I expect that I can get data from Rch and 7, 8, or 9 from Lch.
But, I can't get each value from dataIn16_0 and dataIn16_1 on Expressions window in CCS. I just get same value. For example, I get 7, 8 and 9 on both or I get data from both.
The other trying is this. I get a data two times from RBUF15 to a variables(dataIn16_0, dataIn16_1) in ISR(interrupt service routine by RDATA interrupt working with sys/bios) when I check the slot number(RSLOTCNT in RSLOT).
For example
ISR{
while((CHKBIT(MCASP0->RSLOT, 0x00)));
dataIn16_0 = RBUF15
while((CHKBIT(MCASP0->RSLOT, 0x01)));
dataIn16_1 = RBUF15
:
:
}
I can't get each value from dataIn16_0 and dataIn16_1 on Expressions window in CCS. I can only get value from dataIn16_0 or nothing on the expressions window in CCS.
for more information I put the source.
1. I set the ADC to send(to AXR 15) some data on Rch(when the yellow(LRCK) is high in the picture below.) and nothing on Lch(when the blue(LRCK) is low in the picture below. And the data is only 7,8 or 9. They are fixed on three numbers).(I verify it by an oscilloscope. The picture is attached below.)
2. The frame sync is OK
AHCLKR : 2.048Mhz
ACLKR : 256Khz
AFSR : 8Khz
3. the setting of MCASP receving
uint32_t ak4646_ADC_mcasp_r_init(mcasp_regs_t *mcasp0, mcasp_afifo_reg_t *fifo_r, mcasp_srctl_regs_t *srctl){
// 1. reset mcasp0.
mcasp0->RGBLCTL = 0;
// 2. Configure mcasp0 Audio FIFO. ( Skip )
// if((fifo_r->RFIFOCTL&0x00010000) == 0)
// SETBIT(fifo_r->RFIFOCTL, RENA);
//If the Read FIFO will be enabled, configure RFIFOCTL. Note that RFIFOCTL.RENA should not be set to 1 //(enabled) until the other bitfields in this register are configured.
// 3. Configure all mcasp0 registers.
mcasp0->RMASK = 0x0000FFFF; // Receive data 16bit
mcasp0->RFMT = 0x00018078; // 1-bit delay, MSB, 16bit slot, Peripheral, no rotation.
mcasp0->AFSRCTL = 0x00000113; // 2-slot , Single word, Internally-generated receive frame sync, Falling edge
mcasp0->ACLKRCTL = 0x000000A7; // Rising edge, Internal receive clock. Divide 8: 1.548MHz
mcasp0->AHCLKRCTL = 0x00000000; // External receive high-frequency clock. Divide 1: 2.048000MHz
mcasp0->RTDM = 0x00000003; //0x00000003; // Receive TDM time slot 0,1 Active
mcasp0->RINTCTL = 0x00000020; // Rdata Interrupt
//skip mcasp0->RCLKCHK =
srctl->SRCTL15 = 0x00000022; // Drive low, Serializer receiver.
MCASP0->PFUNC=(0<<31) | (0<<30) | (0<<29) | (1<<25) |(0<<15);
MCASP0->PDIR = 0; // AHCLKR, AHCLKX, AXR(14), (15) : INPUT // ACLKR, ACLKX, AFSR, AFSX, AMUTE : OUTPUT
MCASP0->PDIR=(1<<31) | (0<<30) | (1<<29) | (0<<25)|(0<<15);
mcasp0->DITCTL = 0x00000000;
mcasp0->DLBCTL = 0x00000000;
mcasp0->AMUTE = 0x00000000;
mcasp0->RSTAT = 0x0000FFFF; //Clear all
return (ERR_NO_ERROR);
}
Thanks for your interest and help and regards.
Young