TMS320C6678: PCIE root complex problem - there is link, can access to PCIE configuration space, but cannot access to the bar memory in the End point

Part Number: TMS320C6678

Hi,

I bring up pcie DSP root complex to the Xilinx FPGA ultrascale End point by chip to chip by the board.

I got link, the pcie training is passed and the dsp pcie root can access to "Pcie configuration space" on the FPGA End point.

When try to access by DSP Pcie root to internal memory of the End point its fail and noting is happens.

How I can to debug it?

the Xilinx FPGA ip is https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_1/pg195-pcie-dma.pdf

I configured  bar0 to direct access and bar1 to dma port.

Thanks,

Zvi