Part Number: TCI6638K2K
Hi Eric:
I am a colleague of Ziad. I am actively working in the Serdes test thread now. I followed your suggestion to run the serdes_diag tool on TCI6638K2K Dev kit.It goes well and I already see the result from BER sweep. Here I have some more short question on the BER on PCIe mode results:
1. What is the meanning of pma and cdr in the the BER result(soc_device0_ber_scanout.txt) ? See my txt result below.
| Swing | Deemph | LnErs0 | Bist_Valid0 | Att0 | Boost0 | DFE1_0 | DFE2_0 | DFE3_0 | DFE4_0 | DFE5_0 | CDFE1_0 | CDFE2_0 | CDFE3_0 | CDFE4_0 | CDFE5_0 | CDR0 | PMA0 | DLEVP0 | DLEVN0 | DLEAVG0 |
| 0 | 0 | 0 | 1 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 96 | 521 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 95 | 521 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 96 | 527 | 0 | 0 | 0 |
2. There are 2 lines of source code at csl_serdes2.h accessing peripheral_base_addr (0x21800000)
CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->peripheral_base_addr + 0x180C), 9, 8, serdes_lane_enable_params->num_lanes);
CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->peripheral_base_addr + 0x180C),17,17, 0x1);
Are these required? Can you explain what they did? I removed that at my project it seems like no harm.The reason I remove them is that I can't access this address(bus read error) on Devkit (TCIEVMK2X).