Part Number: TMS320C6678
Hi,
I have a question about the SRIO transmitter swing setting.
My board : there are one C6678 and one FPGA, the SRIO connection between them is four lane, the baudrate is 3.125Gbps, the path setting is 4x mode.
When data transmit from the C6678 to the FPGA, I can see some 8B/10B decode error counts in FPGA's LANE0_STATUS register, and I measure the eye diagram of C6678 TX lane 0, the picture as below, the peak-to-peak voltage is about 200mV. And I checked the swing value in the SERDES_CFGTX0_CNTL register is already 15 (maxim value).
Is the peak-to-peak output voltage of my eye diatram correct? I ask that because I also measure the eye diagram of RX lane 0, the Vpp is about 300mV, it is bigger than TX lane 0. The below picture is RX lane signal.
How can I improve the signal quality?
Thank you,
Snaku