Part Number:AM3505
I have a question regarding the TI AM3505 / AM3517 ( Sitara ) for sustaining a current design.
A bit of background info : the 26 MHz sys_clk is generated by an external oscillator, which is enabled when sys_clkreq asserts from the Sitara.
We also use the power management chip TPS65910. We are in bypass mode as sysboot[6] pulled high.
Schematics are attached.
Question: the 26MHz oscillator has changed startup time specs from 2ms to 8ms ( Abracon AP3S2-26MHz ). Another second-source oscillator has a 10ms out enable delay ( pericom )… is either case a problem ? I think the Sitara comes out of reset after 14ns from 1.8V rail from Vfbio. Does the Sitara use the 26MHz before then ? I think the sys_clkreq is always high, once it gets power ( need to scope this )
Best regards
Egon