Part Number:66AK2H14
Hi,
I have the following DDR3 architecture:
- EMIF controller: 72-bit --> 5 SDRAMs of 16-bit (including 8-bit for ECC)
- Topology: 256M*16,
- Speed: 800MHz,
In my DDR3 Initialization, I program SDCFG register in order to have 8 banks of 1024 words per page.
Where are physically the banks ?
Regards,
François
PS: I do not use any OS, only GEL file.