Part Number:AM3358
From customer:
We are currently performing SI tests on a new design where we are using a TI AM3358 ZCZ.
Timing and signal integrity looks a bit strange on the DDR3 Interface
Below is a measurement of a write data eye DQS1 is orange in the back and the colored data eye is D9.
Interface voltage 1.35V
DQS1: Etch Length is 18.2mm, trace is 80 Ohm Diff
D9 : Etch length 19.3mm, trace is 40 Ohm single
I see in the AM335x errata sheet, that there is an issue with HW read / write leveling, and I also found a TI WIKI describing a procedure for SW R/W leveling.
Currently the SW loads these registers with following value.
DATAx_PHY_RD_DQS_SLAVE_RATIO = 0x38
DATAx_PHY_WR_DQS_SLAVE_RATIO = 0x35
DATAx_PHY_FIFO_WE_SLAVE_RATIO = 0x9D
DATAx_PHY_WR_DATA_SLAVE_RATIO = 0x6F
It is not clear to me if the read/write leveling only affect DDR_CLK to DQS domain, or if it also affects DQ to DQS?
Hope you can help us regarding this issue.
