TCI6638K2K: Performing ATT and BOOST Calibration for PCIe Interface

Part Number:TCI6638K2K

In Errata: KeyStoneII.BTS_errata_usagenote.28 the work around is to perform ATT/BOOST calibration.

We did this successfully for the SRIO interface but for the PCIe interface I am getting really strange results.

Note PCIe interface does not fail all the time. In fact it fails only with High temperature. We are configured for x1 Lane PCIe @ 5.0 Gpbs.

While PCIe is full active and functional I read the following value of the registers:

COMLANE_1F8 : 0x04010000

LN1_OK : 0x0
LN0_OK : 0x0
LN1_SIG_LEVEL_VALID : 0x0
LN0_SIG_LEVEL_VALID : 0x0
CMU_OK : 0x1

PLL_CTRL : 0x10000002

PLL_ENABLE_VAL : 0x0
PLL_OK : 0x1
LN1_OK_STATE : 0x0
LN0_OK_STATE : 0x0
LN1_SD_STATE : 0x1
LN0_SD_STATE : 0x0

Since we are using lane 0 of PCIe phy, and it is fully up and running I am expecting the LN0 values to be set in the above registers.

Furthermore, when I try to read the value for the ATT and BOOST set in the Serdes, I am not able to RXValid for lane0.  The API is in csl_serdes2.h and I am copying it here:

static inline void CSL_SerdesWaitForRXValidPerLane(uint32_t base_addr,
uint8_t lane_num)
{
uint32_t stat;
uint32_t timeout = 100000000;
stat = (CSL_SerdesReadSelectedTbus(base_addr, lane_num+1, 0x2) & 0x020)>>5;
while ((stat != 1) && (timeout != 0))
{
stat = (CSL_SerdesReadSelectedTbus(base_addr, lane_num+1, 0x2) & 0x020)>>5;
timeout--;
}
}

So it seems that there is something special about the PCIe mode for Serdes that is not covered by the documents. Please help.

Ziad A.