We have no OS running on our target hardware.
We want to use USB0 to connect to peripherals. When connecting the peripheral we see the connect interrupt, see debug output below. However it is unclear to me as to how to proceed, do you have an example. I believe after the connect the next step is to reset the peripheral by pulling down the D+,D- lines. Is this correct and how do I do it?
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>>> Resetting the USB controller
DEVCTL = 0x00000098
DEVCTL - B device found
DEVCTL - VBUS above valid
<<< controller reset
>>> Hold PHY in reset for a few clock cycles
<<< Releasing PHY from reset
>>>Wakeup USB module
>>>Wakeup completed
>>> Setting up USB interrupts
<<< USB intterupt setup complete
>>> Start session
DEVCTL = 0x00000019
DEVCTL - A devicefound
DEVCTL - VBUS above valid
DEVCTL - SESSION
ISR:DRVVBUS
<<< Session started....VBUS should be high now
CFGCHIP2 = 0x00032872
CFGCHIP2[17] - Status of USB2.0 PHY - GOOD
CFGCHIP[16]2 - Status of USB2.0 PHY VBUS sense - VBUS voltage found
CFGCHIP2[15] - USB2.0 PHY not in reset
CFGCHIP2[14-13] - USB2.0 OTG subsystem mode - Override phy values to force USB host operation.
CFGCHIP2[12] - USB1.1 PHY reference clock is sourced by output of USB2.0 PHY
CFGCHIP2[11] - USB2.0 PHY reference clock (AUXCLK) is internally generated from the PLL
CFGCHIP2[10] - USB2.0 PHY is enabled and is in operating state (normal operation)
CFGCHIP2[9] - OTG SS is enabled and is in operating state (normal operation)
CFGCHIP2[8] - Differential data polarities are inverted (USB_DP is connected to D- and USB_DM is connected to D+)
CFGCHIP2[7] - Needs to be 0 whenever USB1.1 PHY is unpowered
CFGCHIP2[6] - USB2.0 PHY is prevented from stopping the 48 MHz clock during USB SUSPEND
CFGCHIP2[5] - Session End comparator is enabled
CFGCHIP2[4] - All VBUS line comparators are enabled
CFGCHIP2[3-0] - USB0REF_FREQ 24 MHz
DEVCTL = 0x0000003D
DEVCTL - A devicefound
DEVCTL - Low speed device detected
DEVCTL - VBUS above valid
DEVCTL - HOST mode
DEVCTL - SESSION
ISR:Device Connected