OMAPL138: Cache coherence question between L2 and L1D

My target is an OMAPL138

Tools:

CCS version = 5.1.0

TI compiler = 7.3.1

SYSBIOS = 6.33.1.25

XDCtools = 3.23.0.32

I have data caching turned on in L1D, but not L2 ram.  In my project I'm receiving data via the uPP port placed into L2 ram.  Each uPP "end-of-line" causes an interrupt where I copy and queue the new uPP data for processing.  I've read the document "C647x DSP Cache Users Guide - sprug82a", but still can't convince myself if I need to worry about cache coherence between L2 and L1D?  Do I need to invalidate the location of the new uPP data before I attempt to use it?  Can someone please clarify/explain this for me?  

Thanks in advance,

Dave M