Part Number:DRA80M
Hello E2E community,
My customer is asking generic questions about the DRA80xM device:
What is the value of the series resistor to avoid overshoots and undershoots within the specification?
We want to make sure that the slow, typical and fast models are working with our layout and the series resistor. For this we need the max. and min. allowed voltage for over/undershoots at the RGMII interface with 1V8 and 3V3 IO Supply. I think all have the LVCMOS buffer. The min. high level threshold and the max. low level threshold is available for the LVCMOS buffer.
Checking the Data Manual, Technical Reference Manual and the AM65 product page and "Technical Documents" on www.ti.com, I believe the following is true:
- RGMII is using LVCMOS buffer (Source: SPRSP31A, Data Manual vA, page 22/277 : RGMII balls all show LVCMOS).
- Series resistor value is 22-ohm (Source: SPRACI9.pdf, AM65x / DRA80x Schematic Checklist, Section "2.14 CPSW Ethernet"
- RGMII balls are in the VDDSHV2_WKUP domain (Source: SPRSP31A, Data Manual vA, page 22/277 : RGMII balls all show LVCMOS)
- VDDSHV2_WKUP (therefore RGMII) has min/nom/max range of 1.71V/1.8V/1.89V for 1.8V IO and 3.14V/3.3V/3.46V for 3.3V IO.
- But the Schematic Checklist shows that RGMII is only supported with 1.8V IO (and 3.3V IO is not supported).
Are all these statements correct?
Have I interpreted the data correctly?
Thank you!