Hi：
Recently, I am finding the reason why omapl138 communicate with the NAND chip of MT29F16G08A is so slowly,
When I used the EMIFA port to read or write with the NAND,I found that when i read a byte from the NAND chip to SDRAM,
The CS3 has about 300ns lag,that results bad result about read action.Then i find the linker from this forum:
http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/265264.aspx
So i change the way to read or write with the nand,I used the EDMA of the omapl138,the communication mode is as follows picture:
Because the 4BITECC about the EMIFA port in omapl138 ,each time i write or read 512byte,
I used the channel 0 of EDMA3 to write data from the SRC_ADDR to the NAND port that is 0x62000000,
and used the channel 1 of EDMA3 to read data from the 0x62000000 to the DST_ADDR,In my test ,
I found that when I set the SRC_ADDR and DST_ADDR to the address of SDRAM that from 0x40000000~0x41ffffff,
the read and write is abnormal,but the return value is normal that means the DMA action of read and write is good,
but the data read is wrong, the data read out is not the same with write in,
but when I changed the SRC_ADDR and DST_ADDR to the address of Share Ram (0x80000000~0x8001ffff),
I get the right result,and running about serval hours,no fault find in this time(the data read and write is good that check by CRC check algorithm,if read out is not the same with write in,the LED for test will be extinguish).
I tried change the Master priority about the DSP MDMA from 2 to 0, I still did not get the right result as Share Ram.
1:My question is “Is there any relation about EDMA with CS0?”
2:What reasons about my test result?How can I solved the fault i met.
Thankyou!