OMAPL138 - DDR2 FIFO Queue Questions

Hey L138 Champs,

We'd like to know how deep the FIFO queues are for the SCR on the side of the requested hardware, for example we are accessing DDR2 from both the DSP and the ARM9 core, continuously.

To give you some background we have a device continuously accessing this memory so it is arbitrating very quickly. We are experiencing performance problems with execution speeds.

 1. Is the queue depth infinite?

2. Are there any tools that allow monitoring the performance/usage/depth of these queues?

3. How much latency is involved in pulling memory?

Thanks,