Greetings,
Recently i am facing problem of DSP-RESET when cache is enabled,and i am using cachable ddr2 memory section(using #pragma data_section to place buffer there.)
when cache is disabled my code is working fine.
To make the scenario simple (independent of our waveform code), we tried caching only one buffer.
Having a conditional breakpoint, when 58KB (approx) data is copied, we noticed that non-cached L2 Memory section is corrupted; some are like, vector12, vector13, vector 14, Interrupt handler address, global variables. This will cause uncertainty/exception and DSP will get reset.
Below is the code section and Linker CMD file.
/************************************************************/
main.c File
/***********************************************************/
#pragma DATA_SECTION (tempBuff0, "sdram_bank3");
#pragma DATA_ALIGN (tempBuff0, 128);
uchar tempBuff0[1024*80]={0};
void void_IdleLoop()
{
int ii,jj;
if (ii==1)
{
for (jj=0;jj<1024*80;jj=jj+128)
{
//memcpy(tempBuff0+jj, tempBuff1+jj, 128);
memset(tempBuff0+jj, 55, 128);
}
}
}
/*********************************************************************************
* linker command file for OMAP-L138 DSP code.
**********************************************************************************/
-stack 0x00006000
-heap 0x00002000
MEMORY
{
/*-----------------------------------------------------------------------------
DSP L1 Cache Mem:
-------------------------------------------------------------------------------*/
DSP_L1P_RAM:o = 0x11E00000 l = 0x00008000/*32K*/
DSP_L1D_RAM:o = 0x11F00000 l = 0x00008000/*32K*/
/*-----------------------------------------------------------------------------
Total DSP L2 mem: 0x40000 - 256K
1) entry point
2) 127K L2 P/D Non-Cached
3) 128K L2 P/D Cached
-------------------------------------------------------------------------------*/
entry_point: o = 0x11800000 l = 0x00000080
DSP_L2_RAM_NON_CACHED:o = 0x11800100 l = 0x0001FF00 // 127k
DSP_L2_RAM_CACHED:o = 0x11820000 l = 0x00020000 // 128k
/*-----------------------------------------------------------------------------
Total SHARED mem: 0x20000 - 128K
-------------------------------------------------------------------------------
1) 120KB for ARM.
2) 8KB for DSP.
------------------------------------------------------------------------------*/
SHAREDRAM:o = 0x8001E000 l = 0x00002000 /* 8k */
/*-----------------------------------------------------------------------------
Total DDR2 mem: 0x10000000 - 256MB
-------------------------------------------------------------------------------
1) 6MB for FPGA Bin File.
2) 1MB for DSP AIS executable.
3) 48MB for ARM Core.
4) 1MB for ARM-DSP Communication.
1) 1KB for ARMDSP Pheripheral Control Register.
2) 30KB for ARMDSP Pheripheral Buffers.
3) 100KB Reserved*.
4) 893KB for Message Queue.
5) 200MB for DSP Core.
------------------------------------------------------------------------------*/
/*ARM DSP COMMUNICATION*/
ARM_DSP_REGS:o = 0xC3700000 l = 0x00000400 /* 1 KB */
ARM_DSP_PERIPHERAL_BUFF:o = 0xC3700400 l = 0x00007800 /* 30 KB */
/*RESERVED 100KB*/
IPC_REGISTERS_QUEUES: o = 0xC3720C00 l = 0x000DF400 /* 893 KB */
DDR2:o = 0xC3800000 l = 0x07800000 /* 120 MB */
DDR2_CACHED:o = 0xCB000000 l = 0x05000000 /* 80 MB */
}
SECTIONS
{
.text:_c_int00 > entry_point
.vectors > DSP_L2_RAM_NON_CACHED
.text > DDR2
.const > DDR2
.bss > DSP_L2_RAM_NON_CACHED
.far > DDR2
.switch > DDR2
.stack > DSP_L2_RAM_NON_CACHED
.data > DDR2
.cinit > DDR2
.sysmem > DDR2_CACHED
.cio > DDR2
L2_Convo > DSP_L2_RAM_NON_CACHED //not used
L2_sram > DDR2_CACHED//not used
L2_sram_data > DDR2_CACHED//not used
L1_data > DDR2_CACHED//not used
L1_code > DDR2_CACHED//not used
sdram_bank1 : {} > DDR2_CACHED//not used
sdram_bank2 : {} > DDR2_CACHED//not used
sdram_bank3 : {} > DDR2_CACHED
sdram_bank4 : {} > DDR2_CACHED//not used
}
Plz,help ASAP.
Thanks.