Secure Boot sequence on both ARM and DSP (NOR legacy boot mode)

Hi there

Hope someone can help on this matter.

Consider that we are going to use a secure enabled OMAP-L138 and the NOR legacy boot mode, based on my understanding:

1. The DSP start first and run the DSP ROM bootloader. Meanwhile the ARM is in reset mode (?).
2. The DSP ROM bootloader writes the ARM reset vector via the PRUs
3. The DSP ROM bootloader reads from the NOR flash the DSP Secondary bootloader
   1. The DSP Secondary bootloader is decrypted, authenticated and placed in L2 RAM (as mentioned in the sprugq9, or shared RAM?– as mentioned in the SPRAB41E–January 2014)
4. The DSP Secondary bootloader is executed
   1. The DSP and the ARM images are decrypted, authenticated and placed in mDDR
   2. The ARM is taken out of reset
   3. The DSP goes to sleep (?)
5. The ARM begins the execution of the ARM ROM bootloader
6. The DSP ROM bootloader reads from the NOR flash the ARM Secondary bootloader
7. The ARM Secondary bootloader is executed
   1. The DSP is woken up
   2. Basically a jump to the correct address in mDDR is performed
8. At this stage both ARM and DSP are running

QUESTIONS:

1. Is the above sequence correct?
2. How do we specify the exit mode of the ROM bootloader (NOR legacy is a non-AIS boot mode...)?
3. Can we have ARM and DSP images independently encrypted and signed? I assume we can't if the SK_setUserkey can only be called once per boot!  
4. Could you please confirm the question marks in bold?
5. Does the configuration of the BOOT pins apply to both ARM and DSP?
6. Is there a way to prevent the ARM ROM bootloader to run? Can we modify the ARM reset vector from within the DSP Secondary bootloader so that when the ARM runs it executes immediately the code in the mDDR?

Thanks,

Giuseppe